iPEM

4.8 Gb SDRAM-DDR2

AS4DDR264M72PBG1

AS4DDR264M72PBG1

Rev. 3.1 01/10

13

Micross Components reserves the right to change products or specifications without notice.

EXTENDED MODE REGISTER 2

The extended mode register 2 (EMR2) controls functions

beyond those controlled by the mode register. Currently all

bits in EMR2 are reserved, as shown in Figure 8. The EMR2

is programmed via the LM command and will retain the stored

information until it is programmed again or the device loses

power. Reprogramming the EMR will not alter the contents of

the memory array, provided it is performed correctly.

EMR2 must be loaded when all banks are idle and no bursts are

before initiating any subsequent operation. Violating either of

these requirements could result in unspecified operation.

EXTENDED MODE REGISTER 3

The extended mode register 3 (EMR3) controls functions

beyond those controlled by the mode register. Currently, all

bits in EMR3 are reserved, as shown in Figure 9. The EMR3

is programmed via the LM command and will retain the stored

information until it is programmed again or the device loses

power. Reprogramming the EMR will not alter the contents of

the memory array, provided it is performed correctly.

EMR3 must be loaded when all banks are idle and no bursts

are in progress, and the controller must wait the specifi ed time

t

MRD before initiating any subsequent operation. Violating

either of these requirements could result in unspecified

operation.

COMMAND TRUTH TABLES

The following tables provide a quick reference of DDR2 SDRAM

available commands, including CKE power-down modes, and

bank-to-bank commands.

FIGURE 9 - EXTENDED MODE REGISTER 3 (EMR3) DEFINITION

Notes:

1. E16 (BA2) is only applicable for densities >1Gb, is reserved for future use, and must be pro-

E14

0

1

0

1

Mode Register Set

Mode register (MR)

Extended mode register (EMR)

Extended mode register (EMR2)

Extended mode register (EMR3)

E15

0

0

1

1

A9

A7 A6 A5 A4 A3

A8

A2

A1 A0

Extended mode

register (Ex)

Address bus

97

6

5

4

3

82

1

0

A10

A12 A11

BA0

BA1

10

11

12

n

0

14

15

An

2

MRS

0

0

0

0

0

0

0

0

0

0

0

0

0

BA2

1

16

0

Notes:

1.Mode bits (En) with corresponding address balls (An) greater than A12 are reserved for future use and must be programmed to “0.”

2.E16 (BA2) must be programmed to “0” on this device and is reserved for future use.

1

2