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STM32F745VG bảng dữ liệu(PDF) 176 Page - STMicroelectronics

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Giải thích chi tiết về linh kiện  ARM-based Cortex-M7 32b MCUFPU, 462DMIPS, up to 1MB Flash/32016 4KB RAM, USB OTG HS/FS, ethernet, 18 TIMs, 3 ADCs, 25 com itf, cam & LCD
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STM32F745VG bảng dữ liệu(HTML) 176 Page - STMicroelectronics

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Electrical characteristics
STM32F745xx STM32F746xx
176/227
DocID027590 Rev 4
Synchronous waveforms and timings
Figure 62 through Figure 65 represent synchronous waveforms and Table 96 through
Table 99 provide the corresponding timings. The results shown in these tables are obtained
with the following FMC configuration:
•
BurstAccessMode = FMC_BurstAccessMode_Enable;
•
MemoryType = FMC_MemoryType_CRAM;
•
WriteBurst = FMC_WriteBurst_Enable;
•
CLKDivision = 1;
•
DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM
•
CL = 30 pF on data and address lines. CL = 10 pF on FMC_CLK unless otherwise
specified.
In all timing tables, the THCLK is the HCLK clock period.
–For 2.7 V≤VDD≤3.6 V, maximum FMC_CLK = 108 MHz at CL=20 pF or 90 MHz at
CL=30 pF (on FMC_CLK).
–For 1.71 V≤VDD<2.7 V, maximum FMC_CLK = 70 MHz at CL=10 pF (on FMC_CLK).
1. Guaranteed by characterization results.
Table 95. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings(1)
1. Guaranteed by characterization results.
Symbol
Parameter
Min
Max
Unit
tw(NE)
FMC_NE low time
9THCLK
9THCLK+1.5
ns
tw(NWE)
FMC_NWE low time
7THCLK–0.5
7THCLK+0.5
tsu(NWAIT_NE)
FMC_NWAIT valid before FMC_NEx high
6THCLK+2
-
th(NE_NWAIT)
FMC_NEx hold time after FMC_NWAIT
invalid
4THCLK–1
-



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