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LPS22HB bảng dữ liệu(PDF) 13 Page - STMicroelectronics

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LPS22HB bảng dữ liệu(HTML) 13 Page - STMicroelectronics

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LPS22HB
Mechanical and electrical specifications
49
3.3.2
I2C - inter-IC control interface
Subject to general operating conditions for Vdd and TOP.
Figure 5. I2C slave timing diagram
Note:
Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both ports.
Table 7. I2C slave timing values
Symbol
Parameter (1)
I²C standard mode(1)
I²C fast mode(1)
Unit
Min
Max
Min
Max
f(SCL)
SCL clock frequency
0
100
0
400
kHz
tw(SCLL)
SCL clock low time
4.7
1.3
μs
tw(SCLH)
SCL clock high time
4.0
0.6
tsu(SDA)
SDA setup time
250
100
ns
th(SDA)
SDA data hold time
0.01
3.45
0
0.9
μs
tr(SDA) tr(SCL) SDA and SCL rise time
1000
20 + 0.1Cb(2)
300
ns
tf(SDA) tf(SCL) SDA and SCL fall time
300
20 + 0.1Cb
(2)
300
th(ST)
START condition hold time
4
0.6
μs
tsu(SR)
Repeated START condition
setup time
4.7
0.6
tsu(SP)
STOP condition setup time
4
0.6
tw(SP:SR)
Bus free time between STOP
and START condition
4.7
1.3
1. Data based on standard I2C protocol requirement, not tested in production.
2. Cb = total capacitance of one bus line, in pF.



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