Electrical Characteristics

VCC = CBOOT = 5V, SW = GND = 0V, unless otherwise specified. Typicals and limits appearing in plain type apply for T

A

=T

Symbol

Parameter

Condition

Min

Typ

Max

Units

BOTTOM DRIVER

t

1

Pull-down Delay

Timing Diagram, from

PWM_IN Rising Edge

13

ns

LOGIC

V

uvlo_up

Power On Threshold

VCC rises from 0V toward

5V

2.8

V

V

uvlo_dn

Under-Voltage-Lock-Out

Threshold

2.5

V

V

uvlo_hys

Under-Voltage-Lock-Out

Hysteresis

0.3

V

V

IH_EN

EN Pin High Input

2.4

V

V

IL_EN

EN Pin Low Input

0.25

V

I

leak_EN

EN Pin Leakage Current

EN = VCC = 5V

−2

2

µA

VCC = 5V, EN = 0V

−2

2

t

on_min

Minimum Positive Input

Pulse Width

(Note 4)

55

ns

t

off_min

Minimum Negative Input

Pulse Width

(Note 5)

55

V

IH_PWM

PWM_IN High Level

Input Voltage

When PWM_IN pin goes

high from 0V

2.4

V

V

IL_PWM

PWM_IN Low Level

Input Voltage

When PWM_IN pin goes

low from 5V

0.25

Note 1: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating ratings are conditions under which the device operates

correctly. Operating Ratings do not imply guaranteed performance limits.

ambient thermal resistance,

Note 3: ESD machine model susceptibility is 100V.

Note 4: If after a rising edge, a falling edge occurs sooner than the specified value, the IC may intermittently fail to turn on the bottom gate when the top gate isoff.

As the falling edge occurs sooner and sooner, the driver may start to ignore the pulse and produce no output.

Note 5: If after a falling edge, a rising edge occurs sooner than the specified value, the IC may intermittently fail to turn on the top gate when the bottom gate isoff.

As the rising edge occurs sooner and sooner, the driver may start to ignore the pulse and produce no output.

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