OV7620 datasheet(29/60 Pages) ETC

29 / 60 page

OV7620 Product Specifications - Rev. 1.2 (5/13/00)

OMNIVISION TECHNOLOGIES INC.

Preliminary Company Confidential

AEC<7:0> - exposure time setting; the formula is

Interlaced: TEXPOSURE = TLINE x AEC(7:0);

Progressive: TEXPOSURE = TLINE x AEC(7:0)x2;

where TLINE = Frame Time / 525

if use 27MHz, TLINE = 63.5 uS

Range is: [00] - [7F] for Interlaced; [00] - [FF] for Progressive Scan.

* This register setting is only effective when operated in manual adjust mode (register 13 bit 0=0). Never-

theless, this register is always accessible through the SCCB bus. If register 13 bit 0=1, this

to this register will be useless. The register value can be read out at any time and latest AEC

value will be return. If register 13 bit 0=0, or register 29 bit 7=1, the register will hold last value

unchanged (either input from SCCB or AEC algorithm result).

* It generally takes no more than two fields for the image to reach the intended exposure after changing the

setting.

CLK<5:0> - system clock prescaler; this register defines the chip pixel clock rate, clock rate is defined by

following fulmar:

(16 Bit mode) PCLK = (CLK_input / (( CLK<5:0> + 1) * 2))

(8 Bit mode) PCLK = (CLK_input / ( CLK<5:0> + 1))

SYN<7:6> - Three sync output polarity selection:

SYN7 = 0, SYN6 = 0: HSYNC negative, CHSYNC negative, VSYNC positive edge;

SYN7 = 0, SYN6 = 1:.HSYNC negative, CHSYNC negative, VSYNC negative;

SYN7 = 1, SYN6 = 0: HSYNC positive, CHSYNC negative, VSYNC positive.

SYN7 = 1, SYN6 = 1: HSYNC negative, CHSYNC positive, VSYNC positive.

* The effect of the change is immediate, however, it generally takes about two fields for the image to reach

the stable state

Bits

AEC7

AEC6

AEC5

AEC4

AEC3

AEC2

AEC1

AEC0

Interlace

Progres-

sive Scan

Bits

SYN7

SYN6

CLK5

CLK4

CLK3

CLK2

CLK1

CLK0

Default

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