M68SDIL datasheet(51/460 Pages) MOTOROLA

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Pinout and Signal Descriptions

Signal Descriptions

MC68HC912D60A — Rev 3.0

Technical Data

MOTOROLA

Pinout and Signal Descriptions

ADDR[7:0]

DATA[7:0]

23–16

31–24

External bus pins share function with general-purpose I/O ports A and B.

In single chip modes, the pins can be used for I/O. In expanded modes,

the pins are used for the external buses.

ADDR[15:8]

DATA[15:8]

48–41

64–57

DBE

Data bus control and, in expanded mode, enables the drive control of

external buses during external reads.

ECLK

Inverted ECLK used to latch the address.

CAL

CAL is the output of the Slow Mode programmable clock divider, SLWCLK,

and is used as a calibration reference for functions such as time of day. It

is overridden when DBE function is enabled. It always has a 50% duty

cycle.

CGMTST

Clock generation module test output.

MODB/

IPIPE1,

MODA/

IPIPE0

26, 27

37, 38

State of mode select pins during reset determine the initial operating mode

of the MCU. After reset, MODB and MODA can be configured as

instruction queue tracking signals IPIPE1 and IPIPE0 or as general-

purpose I/O pins.

ECLK

E Clock is the output connection for the external bus clock. ECLK is used

as a timing reference and for address demultiplexing.

LSTRB/

TAGLO

Low byte strobe (0 = low byte valid), in all modes this pin can be used as

I/O. The low strobe function is the exclusive-NOR of A0 and the internal

SZ8 signal. (The SZ8 internal signal indicates the size 16/8 access.) Pin

function TAGLO used in instruction tagging. See Development Support.

R/W

Indicates direction of data on expansion bus. Shares function with

general-purpose I/O. Read/write in expanded modes.

IRQ

Maskable interrupt request input provides a means of applying

asynchronous interrupt requests to the MCU. Either falling edge-

sensitive triggering or level-sensitive triggering is program selectable

(INTCR register).

XIRQ

Provides a means of requesting asynchronous nonmaskable interrupt

requests after reset initialization

SMODN/BK

GD/TAGHI

Single-wire background interface pin is dedicated to the background

debug function. During reset, this pin determines special or normal

operating mode. Pin function TAGHI used in instruction tagging. See

Development Support.

PW[3:0]

80, 1–3

112, 1–3

Pulse Width Modulator channel outputs.

Slave select output for SPI master mode, input for slave mode or master

mode.

SCK

Serial clock for SPI system.

Table 3-2. MC68HC912D60A Signal Description Summary

Pin Name

Pin Number

Description

80-pin

112-pin

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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