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MPI4040R3-2R2-R bảng dữ liệu(PDF) 16 Page - Texas Instruments |
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MPI4040R3-2R2-R bảng dữ liệu(HTML) 16 Page - Texas Instruments |
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16 / 40 page ![]() Temperature (°C) -60 -40 -20 0 20 40 60 80 100 120 140 3 3.5 4 4.5 5 5.5 6 6.5 7 7.5 8 D023 3.3 V 5 V 2 ms/div SW, 5V/div Iinductor, 500mA/div VOUT, 50mV/div 10µs/div 16 LM53602, LM53603 SNVSAR0 – NOVEMBER 2016 www.ti.com Product Folder Links: LM53602 LM53603 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Figure 12. Typical PFM Switching Waveforms Figure 13. Input Voltage for Mode Change 8.4.2 FPWM Mode With a logic high on the FPWM input, the device is locked in PWM mode. This operation is maintained, even at no-load, by allowing the inductor current to reverse its normal direction. This mode trades off reduced light load efficiency for low output voltage ripple, tight output voltage regulation, and constant switching frequency. In this mode, a negative current limit of INEG is imposed to prevent damage to the regulators low-side FET. When in FPWM, the converter synchronizes to any valid clock signal on the SYNC input (see Dropout and Input Voltage Frequency Fold-Back). |
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