CAM35C44 datasheet(29/50 Pages) SMSC

29 / 50 page

TABLE 25 - EXAMPLE POWER CONSUMPTION VS. POWER CONTROL ENABLES

CR08[3:0]

POWER

CONSUMPTION

CLOCK

ACE

SCE

(ICC)

GENERATO

BLOCK

PLL

BLOCK

TYP

MAX

#A4

#A5

(Note

2.5

#A4

#A5

(Note

OFF

500

1mA

RUNNING

OFF

1mA

2mA

RUNNING

OFF

1.6mA

3mA

RUNNING

OFF

6mA

8mA

RUNNING

Note

The 24MHz crystal oscillator directly driving the ACE block enables data transfers up to

115.2Kbps.

Note

The PLL driving the SCE block enables data transfers up to 4Mbps.

Note

PWRGD does not stop the crystal from oscillating if OSC_ON, D0 in configuration register

CR08, is “1”.

Note

PWRGD is “0”.

Note

PWRGD is “1”.

CR09 - Test Control B

The IR_TEST[14:7] bits D0 - D7 in the Test

Control B register enable SMSC internal test

modes. CR09 can only be accessed in the

configuration state and only after the CSR has

been initialized to 09H. The default value of this

IR_TEST[14:7]

bits

are

“0”

(default)

for

normal

operation.

When

any

the

IR_TEST[14:7] bits are “1”, an SMSC internal

test mode is activated. Note: SMSC internal test

modes are reserved for SMSC use, only.

Activating

SMSC

internal

test

modes

may

produce undesired results.

TABLE 26 - TEST CONTROL B REGISTER

DEFAULT

CR09

R/W

IR_TEST[14:7]

0x00

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