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AT91SAM7A1-AI bảng dữ liệu(PDF) 5 Page - ATMEL Corporation

tên linh kiện AT91SAM7A1-AI
Giải thích chi tiết về linh kiện  ARM7TDMI BASED MICROCONTROLLER
PDF  14 Pages
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nhà sản xuất  ATMEL [ATMEL Corporation]
Trang chủ  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

AT91SAM7A1-AI bảng dữ liệu(HTML) 5 Page - ATMEL Corporation

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5
PRELIMINARY
AT91SAM7A1 Summary
6048AS–ATARM–07/04
Pin Description
Table 2. Pin Description
Module
Name
Function
Type
(1)
Level
(1)
Comments
EBI(2)
ADD[19:1]
External address bus
O
(Z)
The EBI is tri-stated when NRESET is
at a logical low level. Internal pull-
downs on data bus bits. ADD20 and
ADD21 are address lines at reset.
ADD0/NLB
External address line/Lower
byte enable
OL (Z)
ADD20/CS7
External address line/Chip
select
OH (Z)
ADD21/CS6
External address line/Chip
select
OH (Z)
D[15:0](3)
External data bus
I/O
(Z)
NOE/NRD
Output enable
O
L (Z)
NWR0/NWE
Write enable
O
L (Z)
NCS[3:0]
Chip select lines
O
L (Z)
NWR1/NUB
Upper byte enable
O
L (Z)
Reserved
Reserved
I
L
Internal pull-up (must be connected to
VCC or leave unconnected for normal
operation)
GIC
IRQ0
External interrupt line
I
FIQ
Fast interrupt line
I
Power-on
Reset
NRESET
Hardware reset input
I
L
Schmitt input with internal filter
Master
Clock
MCKI
Master clock input
I
Connected to external crystal (4 to 16
MHz)
MCKO
Master clock output
O
PLLRC
PLL RC network input
I
Real-time
Clock
RTCKI
32.768 kHz clock input
I
Connected to external 32.768 kHz
crystal
RTCKO
32.768 kHz clock output
O
UPIO
UPIO[17:0]
Unified I/O
I/O (I)
(Z)
General-purpose I/O
USART0
SCK0/MPIO
USART0 clock line
I/O (I)
(Z)
Multiplexed with general-purpose I/O
RXD0/MPIO
USART0 receive line
I/O (I)
(Z)
Multiplexed with general-purpose I/O
TXD0/MPIO
USART0 transmit line
I/O (I)
(Z)
Multiplexed with general-purpose I/O
USART1
SCK1/MPIO
USART1 clock line
I/O (I)
(Z)
Multiplexed with general-purpose I/O
RXD1/MPIO
USART1 receive line
I/O (I)
(Z)
Multiplexed with general-purpose I/O
TXD1/MPIO
USART1 transmit line
I/O (I)
(Z)
Multiplexed with general-purpose I/O
USART2
SCK2/MPIO
USART2 clock line
I/O (I)
(Z)
Multiplexed with general-purpose I/O
RXD2/MPIO
USART2 receive line
I/O (I)
(Z)
Multiplexed with general-purpose I/O
TXD2/MPIO
USART2 transmit line
I/O (I)
(Z)
Multiplexed with general-purpose I/O
Capture
CAPT[1:0]/MPIO
Capture input
I/O (I)
(Z)
Multiplexed with general-purpose I/O
PWM
PWM[3:0]/MPIO
Pulse Width Modulation output
I/O (I)
(Z)
Multiplexed with general-purpose I/O



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