DM9102AT datasheet(36/77 Pages) ETC

36 / 77 page

DM9102A

Single Chip Fast Ethernet NIC controller

Final

Version: DM9102A-DS-F03

August 28, 2000

GEPC

X,RW

GEPD Bits Control

When in initialization, this bit is set and the unique “80h” must be written to the

GEPD(7:0). After initialization, this bit is reset and it controls the functional mode of

GEPD in bit0~7.

GEPD(7)

X,RW

General PHY Reset Control

It must be set to “1” if CR12<8> is set.

When CR12<8> is reset, write “1” to this bit will reset the PHY of the DM9102A.

6:0

GEPD(6:0)

XXXXXXX

,RW

General PHY Status

When CR12<8> is set at initialization, it operates the only write operation and write

the unique “0000000” to these seven bits.

After initialization, CR12<8> is reset, write operation is meaningless and read

these seven bits to indicate the PHY status.

These status bits are shown below.

bit 6:Current Media Link Status

bit 5:Signal Detection

bit 4:RX-lock

bit 3:Internal PHY Link status (the same as bit2 of PHY Register)

bit 2:Full-duplex

bit 1:Speed 100Mbps link

bit 0:Speed 10Mbps link

14. Sample Frame Access Register (CR13) (reference to Power Management section)

987

general definition

bit8 ~ 3

R/W

TxFIFO

transmit FIFO access port

32h

R/W

RxFIFO

receive FIFO access port

35h

R/W

DiagReset general reset for diagnostic pointer port

38h

15. Sample Frame Data Register (CR14) (reference to Power Management section)

987

16. Watchdog and Jabber Timer Register (CR15)

987

Bit

Name

Default

Description

31:25

Reserved

0,RO

Reserved

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