bq2023

SINGLEWIRE ADVANCED BATTERY MONITOR IC

FOR CELLULAR AND PDA APPLICATIONS

SLUS480B – MAY 2001

21

POST OFFICE BOX 655303

APPLICATION INFORMATION

register descriptions (continued)

self-discharge count registers (SCRH/SCRL)

The SCRH high-byte register (address 010B hex) and the SCRL low-byte register (address 010A hex) contain

the self-discharge count. This register is continually updated in both the normal operating and sleep modes of

the bq2023. The counts in these registers are incremented on the basis of time and temperature. The SCR

counts at 1 count per hour at 20–30

°C and doubles every 10°C to greater than 60°C (16 counts/hour). The count

halves every 10

°C below 20–30°C to less than 0°C (1 count/8 hours). These registers continue to count beyond

FFFF hex, so proper register maintenance should be done by the host system. The TMP/CLR register forces

the reset of both the SCRH and SCRL to zero when the SDR bit is set. During device sleep the bq2023 wakes

approximately every hour for 4 seconds to maintain the self-discharge registers.

discharge time count registers (DTCH/DTCL)

The DTCH high-byte register (address 0109 hex) and the DTCL low-byte register (address 0108 hex) determine

4096 counts per hour. If the DTCH/DTCL register continues to count beyond FFFF hex, the STD bit is set in

the MODE/WOE register indicating a rollover. Once set, DTCH and DTCL increment at 16 counts per hour.

NOTE:

If a second rollover occurs, STD is cleared. Access to the bq2023 should be timed to clear

DTCH/DTCL more often than every 170 days. The TEMP/CLR register forces the reset of both the

DTCH and DTCL to zero when the DTC bit is set.

charge time count registers (CTCH/CTCL)

The CTCH high-byte register (address 0107 hex) and the CTCL low-byte register (address 0106 hex) determine

counts per hour. If the CTCH/CTCL registers continue to count beyond FFFF hex, the STC bit is set in the

MODE/WOE register, indicating a rollover. Once set, CTCH and CTCL increment at 16 counts per hour.

NOTE:

If a second rollover occurs, STC is cleared. Access to the bq2023 should be timed to clear

CTCH/CTCL more often than every 170 days. The TMP/CLR register forces the reset of both the

CTCH and CTCL to zero when the CTC bit is set.

mode, wake-up enable register (MOE/WOE)

The Mode/WOE register (address 0105 hex) contains the SLEEP ENABLE bit, the STC and STD bits, and

wake-up enable information as described below:

MODE/WOE BITS

7

6

5

4

3

2

1

0

RSVD

SLEN

STC

STD

WOE2

WOE1

WOE0

RSVD

RSVD

BIT7 is a reserved bit and must always be set to 0. This bit is cleared on Power-on-Reset.

SLEN

The SLEN bit allows the bq2023 to enter sleep mode. The bq2023 enters sleep mode if battery

current (i.e., voltage difference between the SRP and SRN pins) is less than WOE threshold, the SLEN bit is

set, and there is no communication activity on the SDQ pin for approximately one hour. The bq2023 wakes on

either a low-to-high or high-to-low transition on the SDQ pin. The SLEN bit is set during power-on-reset or after

a wake-up condition.

NOTE:

Entering sleep mode does not clear this bit. It must be cleared by the host. This bit is set during

power-on-reset.