Datasheet

Datasheet

17/34

TSZ02201-0F1F0C100240-1-2

© 2013 ROHM Co., Ltd. All rights reserved.

15.Feb.2016 Rev.006

www.rohm.com

TSZ22111・15・001

BD9486F

●3.2.6 UVLO Setting

Under Voltage Lock Out pin is the input voltage of the power stage. IC starts boost operation if UVLO is more than

3.0V(typ.) and stops if lower than 2.7V(typ.).

The UVLO pin is high impedance, because the internal resistance is not connected to a certain bias.

So, the bias by the external components is required, because the open connection of this pin is not a fixed potential.

Detection voltage is set by dividing resistors R1 and R2. The resistor values can be calculated by the formula below.

○UVLO detection equation

○UVLO release equation

R1 and R2 setting is decided by the equation above. The equation of UVLO

release voltage is as follows.

【setting example】

If the normal input voltage, VIN is 24V, the detect voltage of UVLO is 18V, R2 is

30kΩ, R1 is calculated as follows.

]

V

[

]

Ω

k

[

2

R

])

Ω

k

[

2

R

]

Ω

k

[

1

R

(

V

0

.

3







]

Ω

k

[

]

V

[

7

.

2

])

V

[

7

.

2

]

V

[

VIN

(

]

Ω

k

[

2

R

1

R

DET







]

k

[

.

]

V

[

.

])

V

[

.

]

V

[

(

]

k

[

]

V

[

.

])

V

[

.

]

V

[

VIN

(

]

k

[

R

R

DET





















0

170

7

2

7

2

18

30

7

2

7

2

2

1

]

V

[

.

]

V

[

]

k

[

]

k

[

]

k

[

]

V

[

.

]

k

[

R

])

k

[

R

]

k

[

R

(

]

V

[

.

VIN

CAN

0

20

30

30

170

0

3

2

2

1

0

3



























　

Figure 26. UVLO setting example