Data Sheet

VSC8122

Multi-Rate SONET/SDH

Clock and Data Recovery IC

VITESSE

SEMICONDUCTOR CORPORATION

Page 2

G52228-0, Rev 4.1

01/05/01

© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012

Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com

Internet: www.vitesse.com

Functional Description

Data Input

The data input receiver is internally terminated by a center-tapped resistor network. For differential input

and complement of a minimum of 250mV. These inputs are required to be AC-coupled to allow use with a vari-

ety of limiting amplifiers.

Figure 1: Input Termination (AC-Coupled)

High-Speed Clock and Data Outputs

The VSC8122 high-speed clock and data outputs can be DC-terminated, 50

Ω to V

Figure 2.

Figure 2: High-Speed Clock and Data Output DC Termination

VSC8122

Limiting Amp

0.1

µF

0.1

µF

DI+

DI-

50

Ω

50

Ω

VSC8122

50

Ω

50

Ω

100

Ω

100

Ω

CO+ / DO+

CO- / DO-