MCP3918A1-ESLASHSS datasheet(72/88 Pages) MICROCHIP

tên linh kiện	MCP3918A1-E/SS

Giải thích chi tiết về linh kiện	3V Single-Channel Analog Front End

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MCP3918

DS20005287A-page 72

 2014 Microchip Technology Inc.

bit 14

EN_INT:

Enable the CRCREG interrupt function

The interrupt flag for the CRCREG checksum verification is enabled. The Data Ready pin

(DR) will become logic low and stays logic low if a CRCREG checksum error happens. This

interrupt is cleared if the LOCK<7:0> value is made equal to the PASSWORD value (0xA5).

The interrupt flag for the CRCREG checksum verification is disabled. The CRCREG<15:0>

bits are still calculated properly and can still be read in this mode.

bit 13-12

Reserved:

These bits should be kept equal to '0' at all times.

bit 11

EN_MDAT:

Enable Modulator Output

MDAT0 output is enabled

MDAT0 output is disabled (DEFAULT)

bit 10-1

Unimplemented:

Read as ‘0’

bit 0

DRSTATUS:

Data Ready status bit

DRSTATUS

= 1 - Channel CH0 data is not ready (DEFAULT)

DRSTATUS

= 0 - Channel CH0 data is ready. The status bit is set back to '1' after reading the

STATUSCOM register. The status bit is not set back to '1' by the read of the

corresponding channel ADC data.

STATUSCOM REGISTER (CONTINUED)

MCP3918A1-E/SS bảng dữ liệu(PDF) 72 Page - Microchip Technology