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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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CDK8307CILP64 bảng dữ liệu(PDF) 13 Page - Exar Corporation |
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CDK8307CILP64 bảng dữ liệu(HTML) 13 Page - Exar Corporation |
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13 / 31 page  Data Sheet ©2009-2013 Exar Corporation 13/31 Rev 1C Symbol Parameter Conditions Min Typ Max Units Sleep Channel Mode Savings Power dissipation savings per channel off 38 mW Clock Inputs Maximum Conversion Rate 65 MSPS Minimum Conversion Rate 20 MSPS Electrical Characteristics - CDK8307E (AVDD = 1.8V, DVDD = 1.8V, OVDD = 1.8V, 80MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal, 12-bit output, unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units Performance SNR Signal to Noise Ratio FIN = 8MHz 68.5 70.1 dBFS FIN = 30MHz 70 dBFS SINAD Signal to Noise and Distortion Ratio FIN = 8MHz 68 69.6 dBFS FIN = 30MHz 69.5 dBFS SFDR Spurious Free Dynamic Range FIN = 8MHz 74 77 dBc FIN = 30MHz 76 dBc HD2 Second order Harmonic Distortion FIN = 8MHz 85 90 dBc FIN = 30MHz 90 dBc HD3 Third order Harmonic Distortion FIN = 8MHz 75 77 dBc FIN = 30MHz 76 dBc ENOB Effective number of Bits FIN = 8MHz 11.3 bits FIN = 30MHz 11.3 bits Crosstalk See note (1) on page 13 95 dBc Power Supply Analog supply current 173 mA Digital supply current Digital and output driver supply 88 mA Analog power Dissipation 312 mW Digital power Dissipation 158 mW Total power Dissipation 470 mW Power Down Dissipation Power down mode 10 µW Sleep Mode Dissipation Deep sleep mode 56 mW Sleep Channel Mode Dissipation All channels. in sleep ch. mode (light sleep) 116 mW Sleep Channel Mode Savings Power dissipation savings per channel off 44 mW Clock Inputs Maximum Conversion Rate 80 MSPS Minimum Conversion Rate 40 MSPS Digital and Timing Electrical Characteristics (AVDD = 1.8V, DVDD = 1.8V, OVDD = 1.8V, unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units Clock Inputs Duty Cycle 20 80 %high Compliance CMOS, LVDS, LVPECL Input range, differential Differential input swing ±200 mVpp Input range, sine Differential input swing, sine wave clock input ±800 mVpp Input range, CMOS CLKN connected to ground VOVDD mVpp Input common mode voltage Keep voltages within gnd and voltage of OVDD 0.3 VOVDD -0.3 V Input capacitance Differential 2 pF |
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