ML7406 datasheet(45/104 Pages) LAPIS

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FEDL7406-02

ML7406

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(2) In case of using SDI/SDO pin (sharing with SPI interface)

If SDI and SDO pins are used DCLK/DIO, DCLK/DIO is controlled as follow. (below DIO/DCLK vertical line part indicate

output or input.) Both SDO_CFG and SDI_CFG ([SPI/EXT_PA_CTRL:B0 0x53 (5,4)]) should be set 0b1.

[TX]

i) Continuous input mode (from host)

Set TXDIO_CTRL[1:0] ([DIO_SET: B0 0x0C(5-4)])=0b01

After TX_ON(SET_TRX[3:0] ([RF_STATUS: B0 0x0B(3-0)])=0x9), during SCEN pin is ”H”, DCLK is output from SDO pin.

TX data can be input from SDI pin at falling edge of DCLK. TX data must be encoded data. After TRX_OFF is issued

(SET_TRX[3:0] ([RF_STATUS: B0 0x0B(3-0)])=0x8), input data from DIO pin are not valid. During DCLK output, if SCEN

pin becomes “L”, DCLK output will stop. (SPI access has priority)

(Note)

Not to access SPI until TX completion. During packet transmission, if SPI access is attempted by the host, TX data error can

be expected.

ii) Data input mode (from host)

Set TXDIO_CTRL[1:0] ([DIO_SET: B0 0x0C(5-4)])=0b10.

After TX_ON, when SCEN is ”H”, DCLK is output from SDO pin during data input period after SyncWord. At falling edge of

DCLK, TX data should be input to SDI from the host. After TRX_OFF is issued (SET_TRX[3:0] ([RF_STATUS: B0

0x0B(3-0)])=0x8), TX data/clock input/output are invalid. During DCLK output period, if SCEN becomes “L”, DCLK output

will stop. (SPI access has a priority)

(Note)

Not to access SPI until TX completion. During packet transmission, if SPI access is attempted by the host, TX data error can be

expected.

TXON

TX_ON

command

TX data

Preamble

SyncWord

Data-field

TRX_OFF

command

SCEN

DIO(SDI)

TXON

TX_ON

command

TX data

DCLK(SDO)

Preamble

SyncWord

Data-field

TRX_OFF

command

SCEN

DIO(SDI)

DCLK(SDO)

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