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ML7066 bảng dữ liệu(PDF) 6 Page - LAPIS Semiconductor Co., Ltd. |
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ML7066 bảng dữ liệu(HTML) 6 Page - LAPIS Semiconductor Co., Ltd. |
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6 / 29 page ![]() FEDL7066-01 ML7066 6/29 Power Supply Pins Pin No. Pin Name Attribute/ value at reset I/O Active Level Description 34 VREG_IN – – – Power supply pin for regulator. (Typ. 3.0 V) 10 VDD_RF – – – Power supply pin for PA and LNA. Connect to VREG_OUT. (Typ. 2.2V). 25 VDD_VCO – – – Power supply pin for VCO. Connect to VREG_OUT. (Typ. 2.2V) 16 VDD_MIX – – – Power supply pin for mixer 1. Connect to VREG_OUT. (Typ. 2.2V) 31 VDD_CP – – – Power supply pin for charge pump. Connect to VREG_OUT. (Typ. 2.2V) 32 VDD_PLL – – – Power supply pin for PLL. Connect to VREG_OUT. (Typ. 2.2V) 18 VDD_IF – – – Power supply pin for IF, Limiter and RSSI. Connect to VREG_OUT. (Typ. 2.2V) 5, 40 VDDIO – – – Power supply pins for the digital I/O block and internal voltage regulator. (Typ. 3.0 V). 11, 14 20,28 GND_RF_IF – – – Ground pin for RF and IF block. 3,42 GND – – – Ground pin for digital block. EL (*2) – – – – Ground pin (*2) EL is the lower surface of the LSI. |
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