ML7041 datasheet(19/28 Pages) LAPIS

19 / 28 page

FEDL7041-05

ML7041

19/28

FUNCTIONAL DESCRIPTION

Control Registers

CR0 (Basic operating mode 1)

Note: The initial value means a value set when the device is reset by the

PDN pin.

CR0



SEL

SPOUT

PON

PDN

ALL

PDN

SLP

SEL

LNR

Initial value

B7 ....... PCM interface companding law select 0:

-law 1: A-law

B6 ....... Power-on control for output amplifies (SPO+, SPO

) 0: Power down 1: Power on

B5 ....... Power down (entire circuitry)

0: Power on 1: Power down

ORed with the inverted PDN signal. When using this data, set PDN to “L”.

The control registers are not reset by this signal.

B4 ....... Power down (transmit only)

0: Power on 1: Power down

B3 ....... Power down (receive only)

0: Power on 1: Power down

B2 ....... Slope filter enable

0: Slope filter disable 1: Slope filter enable

B1 ....... Slope filter frequency response select 0: CASE1 1: CASE2

Either CASE1 or CASE2 can be selected in Figure 8.

B0 ....... PCM interface linear code select

0: PCM companding law selected by CR0-B7

1: 14-bit linear code (2’s complement)

Figure 8 Slope Filter Frequency Characteristics

–14

–12

–10

–8

–6

–4

–2

500

1000

1500

2000

2500

3000

3500

4000

Frequency [Hz]

CASE1

CASE2

ML7041 bảng dữ liệu(PDF) 19 Page - LAPIS Semiconductor Co., Ltd.

ML7041 bảng dữ liệu(HTML) 19 Page - LAPIS Semiconductor Co., Ltd.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

bảng dữ liệu tải về

Link URL