MCP3909-ESLASHSS datasheet(6/44 Pages) MICROCHIP

6 / 44 page

MCP3909

DS22025C-page 6

 2006-2012 Microchip Technology Inc.

Serial Interface Timings (Note 4)

Data Ready Pulse Width

tDR

4/MCLK

Reset Time

tRST

100

—

Output Data Rate

fADC

—MCLK/256

—

Serial Clock Frequency

fCLK

—20

MHz

VDD = 5V

Window for serial mode entry

codes

tWINDOW

——

32/

MCLK

—

Last bit must be clocked in

before this time.

Window start time for serial

mode entry codes

tWINSET 1/MCLK

—

First bit must be clocked in

after this time.

Serial Clock High Time

tHI

—

fCLK= 20 MHz

Serial Clock Low Time

tLO

—

fCLK= 20 MHz

CS Fall to First Rising CLK Edge

tSUCS

—

Data Input Setup Time

tSU

—

Data Input Hold Time

tHD

—

CS Rise to Output Disable

tDIS

——

150

CLK Rise to Output Data Valid

tDO

—

SDO Rise Time

—2

—

SDO Fall Time

—2

—

TIMING CHARACTERISTICS (CONTINUED)

Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD = DVDD = 4.5V to 5.5V,

AGND, DGND = 0V, MCLK = 3.58 MHz; TA = -40°C to +85°C.

Parameter

Sym

Min

Typ

Max

Units

Comment

Note 1:

If output pulse period (tFP) falls below 984376*2 MCLK periods, then tFW = 1/2 tFP.

If output pulse period (tHP) falls below 322160*2 MCLK periods, then tHW = 1/2 tHP. When F2, F1, F0

equals 0,1,1, the HFOUT pulse time is fixed at 64 x MCLK periods or 18 µs for MCLK = 3.58 MHz.

Specified by characterization, not production tested.

Serial timings specified and production tested with 180 pF load.

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