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P89LPC930 bảng dữ liệu(PDF) 46 Page - NXP Semiconductors |
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P89LPC930 bảng dữ liệu(HTML) 46 Page - NXP Semiconductors |
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46 / 55 page ![]() Philips Semiconductors P89LPC930/931 8-bit microcontrollers with two-clock 80C51 core Product data Rev. 05 — 15 December 2004 46 of 55 9397 750 14472 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Table 9: AC characteristics VDD = 3.0 V to 3.6 V, unless otherwise specified. Tamb = −40 °Cto+85 °C for industrial, unless otherwise specified.[1] Symbol Parameter Conditions Variable clock fosc =18MHz Unit Min Max Min Max fRCOSC internal RC oscillator frequency 7.189 7.557 7.189 7.557 MHz fWDOSC internal Watchdog oscillator frequency 320 520 320 520 kHz fosc oscillator frequency [2] 0 18 - - MHz tCLCL clock cycle see Figure 20 55 - --ns fCLKP CLKLP active frequency 0 8 - - MHz Glitch filter glitch rejection, P1.5/RST pin - 50 - 50 ns signal acceptance, P1.5/RST pin 125 - 125 - ns glitch rejection, any pin except P1.5/RST - 15 - 15 ns signal acceptance, any pin except P1.5/RST 50 - 50 - ns External clock tCHCX HIGH time see Figure 20 22 tCLCL − tCLCX 22 - ns tCLCX LOW time see Figure 20 22 tCLCL − tCHCX 22 - ns tCLCH rise time see Figure 20 -5 - 5 ns tCHCL fall time see Figure 20 -5 - 5 ns Shift register (UART mode 0) tXLXL serial port clock cycle time 16 tCLCL - 888 - ns tQVXH output data set-up to clock rising edge 13 tCLCL - 722 - ns tXHQX output data hold after clock rising edge -tCLCL + 20 - 75 ns tXHDX input data hold after clock rising edge -0 - 0 ns tDVXH input data valid to clock rising edge 150 - 150 - ns SPI interface fSPI Operating frequency 3.0 MHz (Slave) 0 CCLK ⁄6 0 3 MHz 4.5 MHz (Master) - CCLK ⁄4 - 4.5 MHz tSPICYC Cycle time see Figures 15, 16, 17, 18 3.0 MHz (Slave) 6 ⁄CCLK - 333 - ns 4.5 MHz (Master) 4 ⁄CCLK - 222 - ns |
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