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DIT4192IPWR bảng dữ liệu(PDF) 19 Page - Texas Instruments

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tên linh kiện DIT4192IPWR
Giải thích chi tiết về linh kiện  192kHz Digital Audio Transmitter
PDF  22 Pages
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nhà sản xuất  TI [Texas Instruments]
Trang chủ  http://www.ti.com
Logo TI - Texas Instruments

DIT4192IPWR bảng dữ liệu(HTML) 19 Page - Texas Instruments

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DIT4192
19
SBOS229B
www.ti.com
INPUT
FUNCTION
MONO
Stereo/Mono Mode Selection
MONO
Status
0
Stereo Mode
1
Mono Mode
MDAT
Mono Mode Audio and Channel Status Data Selection
MDAT
Status
0
Source is Left Channel for Audio data, and Channel A for CS data.
1
Source is Right Channel for Audio data, and Channel B for CS data.
TABLE IX. Mono Mode Configuration Settings for Hardware Mode Operation.
FIGURE 15. Hardware Mode Example for Dual-Channel Transmitter Operation.
Dual-Wire operation requires that each DIT4192 operates in
Mono mode, which is supported in both Software and Hard-
ware control modes. In Mono mode, the DIT4192 transmits
two consecutive samples of a single channel for both the
Channel A and Channel B sub-frames, effectively doubling
the sampling rate. The audio serial port channel used for
sampling audio and channel status data is selectable in both
Software and Hardware control modes.
In Software mode, the MONO, MDAT, and MCSD bits in
control register 01H are used to select mono mode, as well
as the source channel for audio and channel status data.
Refer to the register definition for details regarding the setting
of these bits.
In Hardware mode, the MONO (pin 21) and MDAT (pin 20)
inputs are used to enable mono mode, as well as selecting
the source channel for audio and channel status data.
Table IX shows the available options for MONO and MDAT
selection. Figure 15 illustrates a simple Hardware mode
configuration for implementing Dual-Channel operation using
two DIT4192 transmitters.
SCLK
SYNC
SDATA
M/S
11
12
13
14
13
12
11
14
TX+
TX–
Right
Channel
Output
Output
Circuit
(See Figs. 12-14)
SDATA
SYNC
SCLK
M/S
TX+
TX–
Left
Channel
Output
Output
Circuit
(See Figs. 12-14)
DIT4192
DIT4192
ADC
DATA
LRCK
BCK
Master Clock
Generator
To All Devices
18
17
18
17
V
IO
21
20
MONO
MDAT
MONO
MDAT
V
IO
21
20
NOTE: To simplify the drawing, not all pins are shown here.



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