CS9211 datasheet(13/62 Pages) NSC

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Revision 2.1

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Signal Definitions (Continued)

2.2.5

Reset, Crystal, and GPIO Pins

Signal Name

Pin No.

Type

(Drive)

Description

RESET#

System Reset Input

A system reset should be at least as long as one clock cycle of the slowest

of DOTCLK, XTALIN or SCLK. RESET# should be active for at least 1 ms.

XTALIN

Crystal Oscillator Connection

This pin is the crystal input for the on-chip reference oscillator or a CMOS

clock input from an external reference source. It should be 14.318 MHz.

XTALOUT

Crystal Oscillator Connection

This pin is the crystal output for the on-chip reference oscillator. If an exter-

nal clock is used, leave this pin unconnected.

GPIO0-GPIO7

70:63

I/O

(4 mA)

General Purpose Inputs/Outputs

Each GPIO pin can be configured independently as an input or output. For

further programming information refer to Section 3.2.13 “General Purpose

I/O Pins” on page 38.

2.2.6

National Semiconductor Internal Test Pins

Signal Name

Pin No.

Type

(Drive)

Description

TEST_SE

Reserved

This pin must be tied to ground for normal operation. It is a National

Semiconductor internal test mode pin only.

MBIST_EN

Reserved

This pin must be tied to ground for normal operation. It is a National

Semiconductor internal test mode pin only.

SCAN_EN

Reserved

This pin must be tied to ground for normal operation. It is a National

Semiconductor internal test mode pin only.

2.2.7

Power and Ground Pins

Signal Name

Pin No.

Type

(Drive)

Description

VDDIO

1, 17, 37,

55, 72,

91, 108,

125

PWR

Power Connection (total of 8 pins)

Power for the DRAM and system interface signals. These pins should be

supplied with 3.3V.

VSSIO

2, 18, 38,

71, 90,

109, 126

GND

Ground Connection (total of 7 pins)

Ground connection.

VDD

36, 73,

144

PWR

Power Connection (total of 3 pins)

Power for the DRAM and system interface signals. These pins should be

supplied with 3.3V.

VSS

19, 54,

89, 128

GND

Ground Connection (total of 4 pins)

Ground connection.

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