COM20022I datasheet(63/83 Pages) SMSC

63 / 83 page

10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM

Datasheet

SMSC COM20022I

Page 63

Rev. 08-18-03

DATASHEET

Figure 8.4

- Multiplexed Bus, 80XX-Like Control Signals; Write Cycle

AD0-AD2,

VALID

nCS

ALE

VALID DATA

t2,

D3-D15

Note 2

t8**

nWR

t10

nRD

t13

t11

t12

nIOCS16

Previous Value

Invalid

Valid Value

t14

Note 3

t15

Parameter

min

max

units

t10

t11

t12

t13

t14

t15

4TARB

Address Setup to ALE Low

Address Hold from ALE Low

nCS Setup to ALE Low

nCS Hold from ALE Low

ALE Low to nDS Low

Valid Data Setup to nDS High

Data Hold from nDS High

ALE High Width

ALE Low Width

nWR Low Width

nWR High Width

nRD

to nWR Low

nIOCS16 Hold Delay from ALE Low

nIOCS16 Output Delay from ALE Low

Cycle Time (nWR

to Next

)**

MUST BE: BUSTMG pin = HIGH

TARB is the Arbitration Clock Period

TARB is identical to Topr if SLOW ARB = 0

TARB is twice Topr if SLOW ARB = 1

Topr is the period of operation clock. It depends on CKUP1 and CKUP0 bits

The Microcontroller typically accesses the COM20022 on every other cycle.

Therefore, the cycle time specified in the microcontroller's datasheet

should be doubled when considering back-to-back COM20022 cycles.

Note 1:

Any cycle occurring after a write to Address Pointer Low Register requires a

minimum of 4TARB from the trailing edge of nWR to the leading edge of the

next nWR.

Note 2:

Write cycle for Address Pointer Low Register occurring after a write to Data

leading edge of the next nWR.

Notes 2 and 3 are applied to an access to Data Register by DMA transfer.

Note 3:

Write cycle for Address Pointer Low Register occurring after a read from Data

leading edge of nWR.

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