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ADP3204JCP bảng dữ liệu(PDF) 15 Page - Analog Devices |
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ADP3204JCP bảng dữ liệu(HTML) 15 Page - Analog Devices |
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15 / 16 page ![]() REV. 0 ADP3204 –15– turned off. During the common off time of all channels, their currents are averaged and compared to the lower threshold. When the averaged channel current reaches the lower threshold, the hysteretic comparator changes state again, and turns on the control FET of the next channel, as selected by the phase splitter logic. This control concept ensures that the peak currents of all channels will be the same, and therefore the CS1 CS2 CS3 VIN PHASE 1 PHASE 2 PHASE 3 L1 L2 L3 RCS1 RCS2 RCS3 RD VREF PHASE SPLITTER HYSTERETIC CORE COMPARATOR CURRENT SENSE MUX LOAD VOUT RE CO RC COC IL1 IL2 IL3 OUT 3 OUT 2 OUT 1 Figure 4. 3-Phase Modified Hysteretic Regulator with ADOPT MathCAD is a trademark of MathSoft. channel currents will be perfectly balanced. The ADOPT compensation can be used the same way as in the single-phase version discussed previously. Since due to second-order effects, the detailed design of a multiphase converter with the ADP320x family is rather complex, a design aid using MathSoft’s MathCAD™ program has been developed. Please contact ADI for further information. |
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