DS3000PE Data Sheet

Control and Status Signals

PWR_GOOD / PWOK

Signal used to indicate that main output voltage is within regulation range. The PWR_GOOD signal will be driven HIGH when the output voltage is valid and will be

driven LOW when the output falls below the under-voltage threshold.

This signal also gives an advance warning when there is an impending power loss due to loss of AC input or system shutdown request. More details in the Timing Section.

This is an open collector/drain output. This pin is pulled high by a 1.0 k ohm resistor connected to 3.3 V inside the power supply. It is recommended that this pin be

connected to a 100 pF decoupling capacitor and pulled down by a 10 k ohm resistor.

MIN

MAX

V

IL

Output logic level LOW

0.8 V

V

IH

Output logic level HIGH

2.0 V

5.0 V

I

SOURCE

Current that may be sourced by this pin

3.3 mA

I

SINK

Current that may be sunk by this pin at low state

0.7 mA

PS_PRESENT

Signal used to indicate to the system that a power supply is inserted in the power bay. Recommended pull-up resistor to 12 VSB is 8.2 k with a 3.0 k pull-down to

ground. A 100 pF decoupling capacitor is also recommended.

PS_INTERRUPT

Active low signal used by the power supply to indicate to the system that a change in power supply status has occurred. This event can be triggered by faults

such as OVP, OCP, OTP, and fan fault. This signal can be cleared by a CLEAR_FAULT command. Recommended pull-up resistor to 12 VSB is 8.2 k with a 3.0 k

pull-down to ground. A 100 pF decoupling capacitor is also recommended.

MIN

MAX

V

IL

Output logic level LOW

0.8 V

V

IH

Output logic level HIGH

2.0 V

5.0 V

I

SOURCE

Current that may be sourced by this pin

4 mA

I

SINK

Current that may be sunk by this pin at low state

4 mA

BUS Signals

ISHARE

Bus signal used by the power supply for active current sharing. All power supplies configured in the system for n+n sharing will refer to this bus voltage inorder to

load share.

Voltage Range

The range of this signal for active sharing will be up to 8.0 V, which corresponds to the maximum output current.

MIN

MAX

I

Input logic level LOW

7.75

8.25

Voltage at 50% load, stand-alone unit

3.85

4.15

Voltage at 0% load, stand-alone unit

0

0.3

I

SOURCE

Current that may be sourced by this pin

160 mA

SCL, SDA

MIN

MAX

V

L

Logic level LOW

0.8 V

V

H

Logic level HIGH

2.0 V

5.0 V

Note: All signal noise levels are below 400 mVpk-pk from 0 - 100 MHz.

FRU ADDRESSING

A2

A1

A0

Address

HIGH

LOW

LOW

0 x A9

HIGH

LOW

HIGH

0 x AB

HIGH

HIGH

LOW

0 x AD

HIGH

HIGH

HIGH

0 x AF*

* Default address when AO and A1 are open

PMBus Addressing

Address

0 x B8

0 x BA

0 x BC

0 x BE