TAS5026 datasheet(39/48 Pages) TI

39 / 48 page

Specifications

SLES041B—November 2002

TAS5026

5.4.2 Serial Audio Port

5.4.2.1

Serial Audio Ports Slave Mode Over Recommended Operating Conditions (Unless

Otherwise Noted)

PARAMETER

MIN

TYP

MAX

UNIT

f(SCLK)

Frequency, SCLK

12.288

MHz

tsu(SDIN)

SDIN setup time before SCLK rising edge

th(SDIN)

SDIN hold time before SCLK rising edge

f(LRCLK)

LRCLK frequency

192

kHz

MCLK_IN duty cycle

50%

SCLK duty cycle

50%

LRCLK duty cycle

50%

tsu(LRCLK)

LRCLK setup time before SCLK rising edge

MCLK High and Low time

5.4.2.2

Serial Audio Ports Master Mode, Load Conditions 50 pF Over Recommended

Operating Conditions (Unless Otherwise Noted)

PARAMETER

MIN

TYP

MAX

UNIT

t(MSD)

MCLK_IN to SCLK

t(MLRD)

MCLK_IN to LRCLK

5.4.2.3

DSP Serial Interface Mode Over Recommended Operating Conditions (Unless

Otherwise Noted)

PARAMETER

MIN

TYP

MAX

UNIT

f(SCLK)

SCLK frequency

12.288

MHz

td(FS)

Delay time, SCLK rising to Fs

tw(FSHIGH)

Pulse duration, sync

1/(64xfs)

tsu(SDIN)

SDIN and LRCLK setup time before SCLK falling edge

th(SDIN)

SDIN and LRCLK hold time from SCLK falling edge

SCLK duty cycle

50%

th(SDIN)

tsu(SDIN)

SCLK

SDIN

Figure 5–6. Right-Justified, IIS, Left-Justified Serial Protocol Timing

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