STLVDS385

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PIN CONFIGURATION

PIN DESCRIPTION

PlN N°

SYMBOL

NAME AND FUNCTION

1, 9, 26

PowerSupplypinsfor TTL Inputs

2, 3, 4, 6, 7, 8, 10, 11, 12,

14, 15, 16, 18, 19, 20, 22,

23, 24, 25, 27, 28, 30, 50,

51, 52, 54, 55, 56

TTL level input. This includes: 8 Red, 8 Green, 8 Blue and 4 control lines-

FPLINE, FPFRAME, and DRDY (also referred to as HSYNC, VSYNC,

Data Enable)

5, 13, 21, 29

GND

Ground pins for TTL Inputs

17

R_FB

Programmable strobe select (See Table 1)

31

TxCLKIN

TTL level clock input. Pin name TxCLK IN

32

PWRDWN

TTL level input. When asserted (low input) TRI-STATES the outputs,

ensuring low current at power down

33, 35

PLL GND

Ground pins for PLL

34

PowerSupplypin forPLL

36, 43, 49

LVDS GND

Ground pins for LVDS outputs

37, 41, 45, 47

TxOUT+

Positive LVDS differential data output

38, 42, 46, 48

TxOUT-

Negative LVDS differential data output

39

TxCLK OUT+

Positive LVDS differential clock output

40

TxCLK OUT-

Negative LVDS differential clock output

44

Power Supply pin for LVDS outputs