ST92196A datasheet(207/268 Pages) STMICROELECTRONICS

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- SERIAL COMMUNICATIONS INTERFACE (SCI)

SERIAL COMMUNICATIONS INTERFACE (Cont’d)

CHARACTER

CONFIGURATION

(CHCR)

R250 - Read/Write

Reset value: undefined

Bit 7 = AM:

Address Mode.

This bit, together with the AMEN bit (in the IDPR

bit/character match operation. Please refer to the

table in the IDPR register description.

Bit 6 = EP:

Even Parity.

0: Select odd parity (when parity is enabled).

1: Select even parity (when parity is enabled).

Bit 5 = PEN:

Parity Enable.

0: No parity bit.

1: Parity bit generated (transmit data) or checked

(received data).

Note: If the address/9th bit is enabled, the parity

bit will precede the address/9th bit (the 9th bit is

never included in the parity calculation).

Bit 4 = AB:

Address/9th Bit.

0: No Address/9th bit.

1: Address/9th bit included in the character format

between the parity bit and the first stop bit. This

bit can be used to address the SCI or as a ninth

data bit.

Bit 3:2 = SB[1:0]:

Number of Stop Bits..

Bit 1:0 = WL[1:0]:

Number of Data Bits

CLOCK CONFIGURATION REGISTER (CCR)

R251 - Read/Write

Reset value: 0000 0000 (00h)

Bit 7:3 = Reserved. Must be left at reset value.

Bit 2 = AEN:

Auto Echo Enable.

0: No auto echo mode.

1: Put the SCI in auto echo mode.

Note: Auto Echo mode has the following effect:

the SCI transmitter is disconnected from the data-

out pin SOUT, which is driven directly by the re-

ceiver data-in pin, SIN. The receiver remains con-

nected to SIN and is operational, unless loopback

mode is also selected.

Bit 1 = LBEN:

Loopback Enable.

0: No loopback mode.

1: Put the SCI in loopback mode.

Note: In this mode, the transmitter output is set to

a high level, the receiver input is disconnected,

and the output of the Transmitter Shift Register is

looped back into the Receiver Shift Register input.

All interrupt sources (transmitter and receiver) are

operational.

Bit 0 = STPEN:

Stick Parity Enable.

0: The transmitter and the receiver will follow the

parity of even parity bit EP in the CHCR register.

1: The transmitter and the receiver will use the op-

posite parity type selected by the even parity bit

EP in the CHCR register.

PEN

SB1

SB0

WL1

WL0

SB1

SB0

Number of stop bits

1.5

2.5

WL1

WL0

Data Length

5 bits

6 bits

7 bits

8 bits

----

AEN

LBEN

STPEN

SPEN

Parity (Transmitter &

Receiver)

0 (odd)

Odd

1 (even)

Even

0 (odd)

Even

1 (even)

Odd

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