TUSB1210 datasheet(13/66 Pages) TI1

13 / 66 page

TUSB1210

www.ti.com

SLLSE09H – NOVEMBER 2009 – REVISED JUNE 2015

4.8.2.2

Timers and Debounce

PARAMETER

COMMENTS

MIN

TYP

MAX

UNIT

TDEL_CS_SUPPLYOK

Chip-select-to-supplies OK delay

2.84

4.10

TDEL_RST_DIR

RESETB to PHY PLL locked and DIR

0.54

0.647

falling-edge delay

TVBBDET

VBAT detection delay

TBGAP

Bandgap power-on delay

TPWONVDD15

VDD15 power-on delay

100

TPWONCK32K

32-KHz RC-OSC power-on delay

125

TDELRSTPWR

Power control reset delay

TDELMNTRVIOEN

Monitor enable delay

91.5

TMNTR

Supply monitoring debounce

183.1

TDELVDD33EN

VDD33 LDO enable delay

93.75

TDELRESETB

RESETB internal delay

244.1

TPLL

PLL lock time

300

4.9

Timing Parameter Definitions

The timing parameter symbols used in the timing requirement and switching characteristic tables are created in

accordance with JEDEC Standard 100. To shorten the symbols, some pin names and other related terminologies

have been abbreviated as shown in Table 4-8.

Table 4-8. Timing Parameter Definitions

LOWERCASE SUBSCRIPTS

SYMBOL

PARAMETER

Cycle time (period)

Delay time

Dis

Disable time

Enable time

Hold time

Setup time

START

Start bit

Transition time

Valid time

Pulse duration (width)

Unknown, changing, or don't care level

High

Low

Valid

Invalid

Active edge

First edge

Last edge

High impedance

Specifications

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