TUSB3200A datasheet(32/102 Pages) TI1

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TUSB3200A

SLES018B – OCTOBER 2001 – REVISED FEBRUARY 2011

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2.2.7.4.1 Isochronous Out Transaction (host PC as source and codec as destination)

The steps to be followed for an isochronous out transaction are as follows:

1. MCU initializes one of the out endpoints as an out isochronous endpoint by programming the

appropriate USB endpoint configuration block. This entails programming the buffer size and the buffer

base address for both the X and Y buffers and the bytes per sample bits, setting the isochronous

endpoint bit, enabling the endpoint, and clearing the NACK bit.

2. The MCU initializes one of the four DMA channels to support the isochronous out endpoint by

programming the appropriate DMA configuration registers.

3. The host PC sends an out token packet followed by a data packet addressed to the out endpoint. The

UBM writes the data packet to the X (or Y) endpoint buffer, updates the sample count in the data count

byte, and sets the X (or Y) buffer NACK bit to a 1. Note that the number of audio samples and not the

number of bytes is written to the data count byte. Also, note that there is no endpoint interrupt

generated for isochronous endpoints. If a buffer overflow occurs, the UBM will set the overflow bit in

the endpoint configuration byte.

4. The DMA channel reads the X (or Y) buffer data count byte to verify that the NACK bit is set and to

obtain the sample count in the new data packet. The DMA channel then clears the NACK bit and

streams the data to the codec port interface. Note that if a new data packet has not been received, the

NACK bit will not be set, and the DMA channel will not move any data to the codec port interface.

2.2.7.4.2 Isochronous Out Transaction (host PC as source and MCU as destination)

The steps to be followed for an isochronous out transaction are as follows:

1. MCU initializes one of the out endpoints as an out isochronous endpoint by programming the

appropriate USB endpoint configuration block. This entails programming the buffer size and the buffer

base address for both the X and Y buffers and the bytes per sample bits, setting the isochronous

endpoint bit, enabling the endpoint, and clearing the NACK bit.

2. The host PC sends an out token packet followed by a data packet addressed to the out endpoint. The

UBM writes the data packet to the X (or Y) endpoint buffer, updates the sample count in the data count

byte, and sets the X (or Y) buffer NACK bit to a 1. Note that the number of audio samples and not the

number of bytes is written to the data count byte. Also, note that there is not an endpoint interrupt

generated for isochronous endpoints. If a buffer overflow occurs, the UBM will set the overflow bit in

the endpoint configuration byte.

3. After an SOF or PSOF interrupt, the MCU reads the USB frame number register and uses the least

significant bit (bit 0) value as the buffer select bit. If bit 0 is a 0 for the current USB frame, then the

MCU should access the Y buffer. If bit 0 is a 1 for the current USB frame, then the MCU should access

the X buffer.

4. The MCU reads the X (or Y) buffer data count byte to verify that the NACK bit is set and to obtain the

sample count in the new data packet. Note that if a new data packet has not been received, the NACK

bit will not be set. If there is a valid data packet in the buffer, then the MCU clears the NACK bit and

proceeds with reading the data.

2.2.7.4.3 Isochronous In Transaction (codec as source and host PC as destination)

The steps to be followed for an isochronous in transaction are as follows:

1. MCU initializes one of the in endpoints as an in isochronous endpoint by programming the appropriate

USB endpoint configuration block. This entails programming the buffer size and the buffer base

address for both the X and Y buffers and the bytes per sample bits, setting the isochronous endpoint

bit, enabling the endpoint, and setting the NACK bit.

2. The MCU initializes one of the four DMA channels to support the isochronous in endpoint by

programming the appropriate DMA configuration registers.

3. During the current USB frame, the DMA proceeds with reading the data from the codec port interface

and storing the data in the X (or Y) endpoint buffer. At the end of the current USB frame, the DMA

updates the sample count in the data count byte then clears the X (or Y) buffer NACK bit to a 0. If a

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