CAT34TS02 datasheet(3/21 Pages) ONSEMI

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CAT34TS02

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Table 5. PIN IMPEDANCE CHARACTERISTICS (VCC = 3.3 V ± 10%, TA = −20°C to +125°C, unless otherwise specified)

Symbol

Parameter

Conditions

Max

Units

CIN

(Note 4)

SDA, EVENT Pin Capacitance

VIN = 0 V, f = 1 MHz

Input Capacitance (other pins)

(Note 5)

Address Input Current (A0, A1, A2)

Product Rev C

VIN < VIH

VIN > VIH

4. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100

and JEDEC test methods.

5. When not driven, the A0, A1 and A2 pins are pulled down to GND internally. For improved noise immunity, the internal pull-down is relatively

strong; therefore the external driver must be able to supply the pull-down current when attempting to drive the input HIGH. To conserve power,

as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x VCC), the strong pull-down reverts to a weak current source.

Table 6. A.C. CHARACTERISTICS (VCC = 3.3 V ± 10%, TA = −20°C to +125°C) (Note 6)

Symbol

Parameter

Min

Max

Units

FSCL (Note 7)

Clock Frequency

400

kHz

tHIGH

High Period of SCL Clock

600

tLOW

Low Period of SCL Clock

1300

tTIMEOUT (Note 7)

SMBus SCL Clock Low Timeout

tR (Note 8)

SDA and SCL Rise Time

300

tF (Note 8)

SDA and SCL Fall Time

300

tSU:DAT (Note 9)

Data Setup Time

100

tSU:STA

START Condition Setup Time

600

tHD:STA

START Condition Hold Time

600

tSU:STO

STOP Condition Setup Time

600

tBUF

Bus Free Time Between STOP and START

1300

tHD:DAT

Input Data Hold Time

tDH (Note 8)

Output Data Hold Time

200

900

Noise Pulse Filtered at SCL and SDA Inputs

100

tWR

Write Cycle Time

tPU (Note 10)

Power−up Delay to Valid Temperature Recording

100

6. Timing reference points are set at 30%, respectively 70% of VCC, as illustrated in Figure 23. Bus loading must be such as to allow meeting

the VIL, VOL as well as the various timing limits.

7. For the CAT34TS02 Rev. B, the TS interface will reset itself and will release the SDA line if the SCL line stays low beyond the tTIMEOUT limit.

The time−out count−down is activated in the interval between START and STOP when SCL is low and is reset while SCL is high. The minimum

clock frequency of 10 kHz is an SMBus recommendation; the minimum operating clock frequency for the CAT34TS02’s SPD component

is DC, while the minimum operating frequency for the TS component is limited only by the SMBus time−out. For the CAT34TS02 Rev. C,

both the TS and the SPD implement the time−out feature.

8. In a “Wired−OR” system (such as I2C or SMBus), SDA rise time is determined by bus loading. Since each bus pull−down device must be

able to sink the (external) bus pull−up current (in order to meet the VIL and/or VOL limits), it follows that SDA fall time is inherently faster than

SDA rise time. SDA rise time can exceed the standard recommended tR limit, as long as it does not exceed tLOW − tDH − tSU:DAT, where tLOW

and tDH are actual values (rather than spec limits). A shorter tDH leaves more room for a longer SDA tR, allowing for a more capacitive bus

or a larger bus pull−up resistor. At the minimum tLOW spec limit of 1300 ns, the maximum tDH of 900 ns demands a maximum SDA tR of 300 ns.

The CAT34TS02’s maximum tDH is <700 ns, thus allowing for an SDA tR of up to 500 ns at minimum tLOW.

9. The minimum tSU:DAT of 100 ns is a limit recommended by standards. The CAT34TS02 will accept a tSU:DAT of 0 ns.

10. The first valid temperature recording can be expected after tPU at nominal supply voltage.

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