PC87382-VBH datasheet(10/72 Pages) NSC

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1.0 Signal/Pin Connection and Description (Continued)

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Revision1.2

1.3

DETAILED SIGNAL/PIN DESCRIPTIONS

This section describes all signals of the PC87382.

1.3.1

LPC Bus Interface

1.3.2

Docking LPC Bus

1.3.3

Clocks

Signal

Pin(s)

I/O

Buffer Type

Description

LAD3-0

40, 38,

36, 32

I/O

INPCI/OPCI

LPC Address-Data. Multiplexed command, address bidirectional data

and cycle status.

LCLK

INPCI

LPC Clock. Same as PCI clock (up to 33 MHz).

LDRQ

OPCI

LPC DMA Request. Encoded DMA request for LPC interface.

LFRAME

INPCI

LPC Frame. Low pulse indicates the beginning of a new LPC cycle or

termination of a broken cycle.

LRESET

INPCI

LPC Reset. Same as PCI system reset.

SERIRQ

I/O

INPCI/OPCI

Serial IRQ. The interrupt requests are serialized over a single pin, where

each IRQ level is delivered during a designated time slot.

CLKRUN

I/OD

INPCI/OD6

Clock Run. Same as PCI CLKRUN.

Signal

Pin(s)

I/O

Buffer Type

Description

DLAD3-0

41, 39,

37, 33

I/O

Dock LPC Address-Data. Multiplexed command, address bidirectional

data and cycle status.

DLCLK

I/O

Dock LPC Clock. Same as PCI clock (up to 33 MHz).

DLFRAME

I/O

Dock LPC Frame. Low pulse indicates the beginning of a new LPC cycle

or termination of a broken cycle.

DSERIRQ

I/O

Dock Serial IRQ. The interrupt requests are serialized over a single pin,

where each IRQ level is delivered during a designated time slot.

DCLKRUN

I/O

Dock Clock Run. Same as PCI CLKRUN.

DLRESET

O4/4

Dock LPC Reset. Main LPC Reset combined with Dock LPC enable.

DLDRQ

INT

Dock LPC DMA Request. Encoded DMA request for LPC interface.

Signal

Pin(s)

I/O

Buffer Type

Description

CLKIN

INT

Clock In. 14.318 MHz or 48 MHz clock input.

DCLKOUT

O14/14

Dock Clock Output. Buffered clock for the Docking device. Enabled

together with DLCLK; otherwise in TRI-STATE.

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