PC87382 datasheet(37/72 Pages) NSC

37 / 72 page

Revision 1.2

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4.0

LPC Bus Interface

4.1

OVERVIEW

The LPC host Interface supports 8-bit I/O Read and Write and 8-bit DMA transactions, as defined in Intel’s LPC Interface

Speciﬁcation, Revision 1.1.

4.2

LPC TRANSACTIONS

The LPC Interface of the PC87382 can respond to the following LPC transactions:

8-bit I/O read and write cycles

8-bit DMA read and write cycles

DMA request cycles

4.3

CLKRUN FUNCTIONALITY

The PC87382 supports the CLKRUN signal, which is implemented according to the specification in PCI Mobile Design

Guide, Revision 1.1, December 18, 1998. The PC87382 supports operation with both a slow and stopped clock in ACPI state

S0 (when the system is active but is not being accessed). In the following cases, the PC87382 drives the CLKRUN signal

low to force the LPC bus clock into full speed operation:

An IRQ is pending internally, waiting to be sent through the serial IRQ.

A DMA request is pending internally, waiting to be sent through the serial DMA.

Note: When the CLKRUN signal is not in use, the PC87382 assumes a valid clock on the LCLK pin.

4.4

INTERRUPT SERIALIZER

The Interrupt Serializer translates parallel interrupt request signals received from internal IRQ sources, into serial interrupt

request data transmitted over the SERIRQ bus.

The internal IRQs are fed into a Mapping, Enable and Polarity Control block, which maps them to their associated IRQ slots.

The IRQs are then fed into the Interrupt Serializer, where they are translated into serial data and transmitted over the SER-

IRQ bus.

The same slot cannot be shared among different interrupt sources in the device.

PC87382 bảng dữ liệu(PDF) 37 Page - National Semiconductor (TI)