EMC1184 datasheet(13/48 Pages) MICROCHIP

13 / 48 page

Quad Channel 1°C Temperature Sensor with Beta Compensation and 1.8V SMBus Communications

Datasheet

SMSC EMC1184

Revision 1.0 (07-11-13)

DATASHEET

Chapter 4 System Management Bus Interface Protocol

4.1

Communications Protocol

The EMC1184 communicates with a host controller, such as an SMSC SIO, through the SMBus. The

SMBus is a two-wire serial communication protocol between a computer host and its peripheral

devices. A detailed timing diagram is shown in Figure 4.1.

For the first 15ms after power-up the device may not respond to SMBus communications.

4.1.1

SMBus Start Bit

The SMBus Start bit is defined as a transition of the SMBus Data line from a logic ‘1’ state to a logic

‘0’ state while the SMBus Clock line is in a logic ‘1’ state.

4.1.2

SMBus Address and RD / WR Bit

The SMBus Address Byte consists of the 7-bit client address followed by the RD / WR indicator bit. If

this RD / WR bit is a logic ‘0’, the SMBus Host is writing data to the client device. If this RD / WR bit

is a logic ‘1’, the SMBus Host is reading data from the client device.

The EMC1183-A and EMC1184-A SMBus slave address is determined by the pull-up resistor on the

THERM pin as shown in Table 4.1, "SMBus Address Decode".

The Address decode is performed by pulling known currents from VDD through the external resistor

causing the pin voltage to drop based on the respective current / resistor relationship. This pin voltage

is compared against a threshold that determines the value of the pull-up resistor.

Figure 4.1 SMBus Timing Diagram

Table 4.1 SMBus Address Decode

PULL UP RESISTOR ON

THERM PIN (±5%)

SMBUS ADDRESS

4.7k

1111_100(r/w)b

6.8k

1011_100(r/w)b

SMDATA

SMCLK

BUF

S - Start Condition

P - Stop Condition

T HIGH

T LOW

HD:STA

SU:STO

HD:STA

HD:DAT

SU:DAT

SU:STA

FALL

RISE

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