EMC1187 datasheet(35/47 Pages) MICROCHIP

35 / 47 page

Triple Channel 1°C Temperature Sensor with Hardware Thermal Shutdown and 1.8V SMBus Communications

Datasheet

SMSC EMC1187

Revision 1.0 (07-11-13)

DATASHEET

6.12

Channel Mask Register 1Fh

The Channel Mask Register controls individual channel masking. When a channel is masked, the

ALERT pin will not be asserted when the masked channel reads a diode fault or out of limit error. The

channel mask does not mask the SYS_SHDN pin.

Bit 2 - E2MASK - Masks the ALERT pin from asserting when the External Diode 2 channel is out of

limit or reports a diode fault.



‘0’ (default) - The External Diode 2 channel will cause the ALERT pin to be asserted if it is out of

limit or reports a diode fault.



‘1’ - The External Diode 2 channel will not cause the ALERT pin to be asserted if it is out of limit

or reports a diode fault.

Bit 1 - E1MASK - Masks the ALERT pin from asserting when the External Diode1 channel is out of

limit or reports a diode fault.



‘0’ (default) - The External Diode1 channel will cause the ALERT pin to be asserted if it is out of

limit or reports a diode fault.



‘1’ - The External Diode1 channel will not cause the ALERT pin to be asserted if it is out of limit

or reports a diode fault.

Bit 0 - INTMASK - Masks the ALERT pin from asserting when the Internal Diode temperature is out

of limit.



‘0’ (default) - The Internal Diode channel will cause the ALERT pin to be asserted if it is out of limit.



‘1’ - The Internal Diode channel will not cause the ALERT pin to be asserted if it is out of limit.

6.13

Consecutive ALERT Register 22h

The Consecutive ALERT Register determines how many times an out-of-limit error or diode fault must

be detected in consecutive measurements before the ALERT or SYS_SHDN pin is asserted.

Additionally, the Consecutive ALERT Register controls the SMBus Timeout functionality.

An out-of-limit condition (i.e. HIGH, LOW, or FAULT) occurring on the same temperature channel in

consecutive measurements will increment the consecutive alert counter. The counters will also be reset

if no out-of-limit condition or diode fault condition occurs in a consecutive reading.

When the ALERT pin is configured as an interrupt, when the consecutive alert counter reaches its

programmed value, the following will occur: the STATUS bit(s) for that channel and the last error

condition(s) (i.e. E1HIGH or E2LOW and/or E2FAULT) will be set to ‘1’, the ALERT pin will be asserted,

the consecutive alert counter will be cleared, and measurements will continue.

Table 6.13 Channel Mask Register

ADDR.

R/W

DEFAULT

1Fh

R/W

Channel

Mask

---

MASK

INT

MASK

00h

Table 6.14 Consecutive ALERT Register

ADDR.

R/W

DEFAULT

22h

R/W

Consecutive

ALERT

TIME

OUT

CTHRM[2:0]

CALRT[2:0]

70h

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