TSB81BA3DPFP datasheet(33/61 Pages) TI1

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TSB81BA3D, TSB81BA3DI

IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER

SLLS559E − DECEMBER 2002 − REVISED JUNE 2006

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION (1394a−2000 INTERFACE)

status transfer

A status transfer is initiated by the PHY when there is status information to be transferred to the LLC. The PHY

waits until the interface is idle before starting the transfer. The transfer is initiated by the PHY asserting status

(01b) on the CTL terminals, along with the first two bits of status information on the D[0:1] terminals. The PHY

maintains CTL = Status for the duration of the status transfer. The PHY may prematurely end a status transfer

by asserting something other than status on the CTL terminals. This occurs if a packet is received before the

status transfer completes. The PHY continues to attempt to complete the transfer until all status information has

been successfully transmitted. There is at least one idle cycle between consecutive status transfers.

The PHY normally sends just the first 4 bits of status to the LLC. These bits are status flags that are needed

by the LLC state machines. The PHY sends an entire 16-bit status packet to the LLC after a read register

request, or when the PHY has pertinent information to send to the LLC or transaction layers. The only defined

condition where the PHY automatically sends a register to the LLC is after self-ID, where the PHY sends the

physical-ID register that contains the new node address. All status transfers are either 4 or 16 bits unless

interrupted by a received packet. The status flags are considered to have been successfully transmitted to the

LLC immediately upon being sent, even if a received packet subsequently interrupts the status transfer. Register

contents are considered to have been successfully transmitted only when all 8 bits of the register have been

sent. A status transfer is retried after being interrupted only if any status flags remain to be sent, or if a register

transfer has not yet completed.

Table 19 shows the definition of the bits in the status transfer and Figure 12 shows the timing.

Table 19. Status Bits

BIT(s)

NAME

DESCRIPTION

Arbitration reset gap

Indicates that the PHY has detected that the bus has been idle for an arbitration reset gap time (as defined in

the IEEE 1394a−2000 standard). This bit is used by the LLC in the busy/retry state machine.

Subaction gap

Indicates that the PHY has detected that the bus has been idle for a subaction gap time (as defined in the

IEEE 1394a−2000 standard). This bit is used by the LLC to detect the completion of an isochronous cycle.

Bus reset

Indicates that the PHY has entered the bus reset state

Interrupt

Indicates that a PHY interrupt event has occurred. An interrupt event may be a configuration time-out, a

cable-power voltage falling too low, a state time-out, or a port status change.

4−7

Address

This field holds the address of the PHY register whose contents are being transferred to the LLC

8−15

Data

This field holds the register contents

(a)

(b)

S[14:15]

S[0:1]

D0, D1

CTL0, CTL1

SYSCLK

Figure 12. Status Transfer Timing

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