Vias to the

internal SW

node copper

EN

VFB

VBST

GND

SW

FEEDBACK

RESISTORS

TO ENABLE

CONTROL

VIN

GND

BOOST

CAPACITOR

OUTPUT

INDUCTOR

OUTPUT

CAPACITOR

VOUT

INPUT BYPASS

CAPACITOR

VIN

SW node copper

pour area on internal

or bottom layer

Additional

Vias to the

GND plane

HIGH FREQUENCY

INPUT BYPASS

CAPACITOR

Vias to the

internal SW

node copper

SS

PG

SLOW START

CAPACITOR

VIA TO INTERNAL

GROUND PLANE

PG PULL UP

RESISTOR

POWER GOOD

TO PG PULL

UP VOLTAGE

TPS56x210

TPS562210, TPS563210

SLVSCM6A – FEBRUARY 2015 – REVISED AUGUST 2015

www.ti.com

11 Layout

11.1 Layout Guidelines

1. VIN and GND traces should be as wide as possible to reduce trace impedance. The wide areas are also of

advantage from the view point of heat dissipation.

2. The input capacitor and output capacitor should be placed as close to the device as possible to minimize

trace impedance.

3. Provide sufficient vias for the input capacitor and output capacitor.

4. Keep the SW trace as physically short and wide as practical to minimize radiated emissions.

5. Do not allow switching current to flow under the device.

6. A separate VOUT path should be connected to the upper feedback resistor.

7. Make a Kelvin connection to the GND pin for the feedback path.

8. Voltage feedback loop should be placed away from the high-voltage switching trace, and preferably has

ground shield.

9. The trace of the VFB node should be as small as possible to avoid noise coupling.

10. The GND trace between the output capacitor and the GND pin should be as wide as possible to minimize its

trace impedance.

11.2 Layout Example

24

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