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AFE1302Y/2K bảng dữ liệu(PDF) 6 Page - Texas Instruments

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AFE1302Y/2K bảng dữ liệu(HTML) 6 Page - Texas Instruments

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AFE1302
6
SBWS014
FIGURE 2. AFE1302 Transmit/Receive Timing Diagram.
RX[0:3]/TX[0:3]
CLKM/CLKNIB
CLWD
N0
N1
t
S
t
H
N2
N3
NOTE: CLKM = 35.328; For N = 1, CLKNIB = 35.328MHz, CLWD = 8.832MHz; t
S: Setup Time, min tS = 5ns; tH: Hold Time, min tH = 5ns.
TRANSMIT DATA
Transmit data TX[0:3] passed to the AFE1302 will be
Binary Two’s Complement with one or two sign bits de-
pending on bit 9 in the AFE1302 control register at address
001 (see Table V). Bit 9 = 0 is two sign bits and bit 9 = 1
is one sign bit. Please refer to Tables I and II.
TABLE I. AFE1302 TX Data Format, Address 001, Bit 9 = 0.
BIT MAP\NIBBLE
N0
N1
N2
N3
TX0
data bit 0 (LSB)
data bit 4
data bit 8
data bit 12
TX1
data bit 1
data bit 5
data bit 9
data bit 13
TX2
data bit 2
data bit 6
data bit 10
data sign
TX3
data bit 3
data bit 7
data bit 11
data sign
TABLE II. AFE1302 TX Data Format, Address 001, Bit 9 = 1.
BIT MAP\NIBBLE
N0
N1
N2
N3
TX0
data bit 0 (LSB)
data bit 4
data bit 8
data bit 12
TX1
data bit 1
data bit 5
data bit 9
data bit 13
TX2
data bit 2
data bit 6
data bit 10 data bit 14
TX3
data bit 3
data bit 7
data bit 11
data sign
This corresponds to the internal data structure as follows:
TABLE III. AFE1302 RX Data Format, Address 001,
Bit 9 = 0.
BIT MAP\NIBBLE
N0
N1
N2
N3
RX0
data bit 0 (LSB)
data bit 4
data bit 8
data bit 12
RX1
data bit 1
data bit 5
data bit 9
data bit 13
RX2
data bit 2
data bit 6
data bit 10
data sign
RX3
data bit 3
data bit 7
data bit 11
data sign
This corresponds to the internal data structure as follows
(sign bit is repeated):
TABLE IV. AFE1302 RX Data Format, Address 001, Bit 9 = 1.
BIT MAP\NIBBLE
N0
N1
N2
N3
RX0
data bit 0 (LSB)
data bit 4
data bit 8
data bit 12
RX1
data bit 1
data bit 5
data bit 9
data bit 13
RX2
data bit 2
data bit 6
data bit 10 data bit 14
RX3
data bit 3
data bit 7
data bit 11
data sign
This corresponds to the internal data structure as follows:
This corresponds to the internal data structure as follows
(sign bit is repeated):
RECEIVE DATA
Data RX[0:3] received from the AFE1302 will be in the
format shown in Tables III and IV:
INTERNAL DATA BIT
15
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTERNAL DATA BIT
Sign Sign 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INTERNAL DATA BIT
15
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTERNAL DATA BIT
Sign 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INTERNAL DATA BIT
Sign Sign 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTERNAL DATA BIT
15
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INTERNAL DATA BIT
Sign 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTERNAL DATA BIT
15
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0



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