ADS1216

18

SBAS171B

RDATA

Read Data

Description: Read a single data value from the Data Output

Register (DOR) which is the most recent conversion result.

This is a 24-bit value.

Operands:

None

Bytes:

1

Encoding:

0000 0001

Data Transfer Sequence:

COMMANDS

DESCRIPTION

COMMAND BYTE

2ND COMMAND BYTE

RDATA

Read Data

—

RDATAC

Read Data Continuously

—

STOPC

Stop Read Data Continuously

—

RREG

Read from REG Bank “rrrr”

xxxx_nnnn (# of reg-1)

RRAM

Read from RAM Bank “aaa”

xnnn_nnnn (# of bytes-1)

CREG

Copy REGs to RAM Bank “aaa”

—

CREGA

Copy REGS to all RAM Banks

—

WREG

Write to REG “rrrr”

xxxx_nnnn (# of reg-1)

WRAM

Write to RAM Bank “aaa”

xnnn_nnnn (# of bytes-1)

CRAM

Copy RAM Bank “aaa” to REG

—

CSRAMX

Calc RAM Bank “aaa” Checksum

—

CSARAMX

Calc all RAM Bank Checksum

—

CSREG

Calc REG Checksum

—

CSRAM

Calc RAM Bank “aaa” Checksum

—

CSARAM

Calc all RAM Banks Checksum

—

SELFCAL

Self Cal Offset and Gain

—

SELFOCAL

Self Cal Offset

—

SELFGCAL

Self Cal Gain

—

SYSOCAL

Sys Cal Offset

—

SYSGCAL

Sys Cal Gain

—

DSYNC

Sync DRDY

—

SLEEP

Put in SLEEP Mode

—

RESET

Reset to Power-Up Values

—

NOTE: (1) The data received by the A/D is always MSB First, the data out format is set by the BIT ORDER bit in ACR reg.

TABLE III. Command Summary.

RDATAC

Read Data Continuous

Description: Read Data Continuous mode enables the con-

tinuous output of new data on each DRDY. This command

eliminates the need to send the Read Data Command on each

DRDY. This mode may be terminated by either the STOP

Read Continuous command or the RESET command.

Operands:

None

Bytes:

1

Encoding:

0000 0011

Data Transfer Sequence:

Command terminated when “uuuu uuuu” equals STOPC

or RESET.

ADS1216 CONTROL

COMMAND DEFINITIONS

The commands listed below control the operation of the

ADS1216. Some of the commands are stand-alone com-

mands (e.g., RESET) while others require additional bytes

(e.g., WREG requires command, count, and the data bytes).

cycles before the data is ready (e.g., RDATA).

Operands:

n = count (0 to 127)

r = register (0 to 15)

x = don’t care

a = RAM bank address (0 to 7)

D

IN

0000 0001

xxxx xxxx

xxxx xxxx

xxxx xxxx

D

OUT

NOTE: (1) For wait time, refer to timing specification.

xxxx xxxx

MSB

Mid-Byte

LSB

D

IN

• • •

0000 0011

uuuu uuuu

uuuu uuuu

uuuu uuuu

D

OUT

xxxx xxxx

MSB

Mid-Byte

LSB

D

IN

xxxx

xxxx

D

OUT

MSB

Mid-Byte

xxxx

LSB

DRDY

• • •

• • •

NOTE: (1) For wait time, refer to timing specification.