1°C Triple Temperature Sensor with Resistance Error Correction & Hotter of Two Zones

Datasheet

SMSC EMC1053

9

Revision 1.44 (04-14-08)

DATASHEET

Note 2.1

300nS rise time max is required for 400kHz bus operation. For lower clock frequencies,

Note 2.2

See SMSC Applications for Application Notes and Guidelines when measuring GPU

processor diodes and CPU processor diodes.

2.3

System Management Bus Interface Protocol

A host controller, such as an SMSC I/O controller, communicates with the EMC1053 via the two wire

serial interface named SMBus. The SMBus interface is used to read and write registers in the

EMC1053, which is a slave-only device. A detailed timing diagram is shown in Figure 2.1.

Figure 2.1 System Management Bus Timing Diagram

The EMC1053 implements a subset of the SMBus specification and supports Write Byte, Read Byte,

Send Byte, and Receive Byte protocols as shown. In the tables that describe the protocol, the “gray”

columns indicate that the slave is driving the bus.

All of the below protocols use the following convention:

2.3.1

Write Byte

The Write Byte is used to write one byte of data to the registers as shown in Table 2.3.

2.3.2

Read Byte

The Read Byte protocol is used to read one byte of data from the registers as shown in Table 2.4.

DATA SENT

TO DEVICE

DATA SENT TO

THE HOST

# of bits sent

# of bits sent

Table 2.3 Write Byte Protocol

START

SLAVE ADDRESS

WR

ACK

COMMAND

ACK

DATA

ACK

STOP

17

1

18

18

11

Table 2.4 Read Byte Protocol

START

SLAVE

ADDRESS

WR

ACK

COMMAND

ACK

START

SLAVE

ADDRESS

RD

ACK

DATA

NACK

STOP

SMDATA

SMCLK

T

LOW

T

R

T

HIGH

T

F

T

BUF

T

HD:STA

P

S

S - Start Condition

P - Stop Condition

T

T

SU:STA

T

HD:STA

P

T

SU:STO

S