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ST72561 bảng dữ liệu(PDF) 35 Page - STMicroelectronics |
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ST72561 bảng dữ liệu(HTML) 35 Page - STMicroelectronics |
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35 / 262 page ![]() ST72561 35/262 INTERRUPTS (Cont’d) Table 8. Interrupt Mapping Notes: 1. Valid for HALT and ACTIVE-HALT modes except for the MCC/RTC interrupt source which exits from ACTIVE-HALT mode only. 2. Except AVD interrupt 3. Exit from Halt only when a wake-up condition is detected, generating a Status Change interrupt. See Section 10.9.5 on page 187. 4. It is possible to exit from Halt using the external interrupt which is mapped on the RDI pin. N° Source Block Description Register Label Priority Order Exit from HALT1) Address Vector RESET Reset N/A Highest Priority Lowest Priority yes FFFEh-FFFFh TRAP Software interrupt no FFFCh-FFFDh 0 TLI External top level interrupt EICR yes FFFAh-FFFBh 1 MCC/RTC Main clock controller time base interrupt MCCSR yes FFF8h-FFF9h 2 ei0/AWUFH External interrupt ei0/ Auto wake-up from Halt EICR/ AWUCSR yes2) FFF6h-FFF7h 3 ei1/AVD External interrupt ei1/Auxiliary Voltage Detector EICR/ SICSR FFF4h-FFF5h 4 ei2 External interrupt ei2 EICR FFF2h-FFF3h 5 ei3 External interrupt ei3 EICR FFF0h-FFF1h 6 CAN CAN peripheral interrupt - RX CIER no FFEEh-FFEFh 7 CAN CAN peripheral interrupt - TX / ER / SC CIER yes3) FFECh-FFEDh 8 SPI SPI peripheral interrupts SPICSR yes FFEAh-FFEBh 9 TIMER8 8-bit TIMER peripheral interrupts T8_TCR1 no FFE8h-FFE9h 10 TIMER16 16-bit TIMER peripheral interrupts TCR1 no FFE6h-FFE7h 11 LIN SCI2 LINSCI2 Peripheral interrupts SCI2CR1 no FFE4h-FFE5h 12 LIN SCI1 LINSCI1 Peripheral interrupts (LIN Master/ Slave) SCI1CR1 no4) FFE2h-FFE3h 13 PWM ART 8-bit PWM ART interrupts PWMCR yes FFE0h-FFE1h |
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