ST72561 datasheet(197/262 Pages) STMICROELECTRONICS

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ST72561

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beCAN CONTROLLER (Cont’d)

CAN RECEIVE FIFO REGISTERS (CRFR)

Read / Write

Reset Value: 0000 0000 (00h)

Note: To clear a bit in this register, software must

write a “1” to the bit.

Bit 7:6 = Reserved. Forced to 0 by hardware.

Bit 5 = RFOM Release FIFO Output Mailbox

- Read/Set

Set by software to release the output mailbox of

the FIFO. The output mailbox can only be released

when at least one message is pending in the FIFO.

Setting this bit when the FIFO is empty has no ef-

fect. If more than one message are pending in the

FIFO, the software has to release the output mail-

box to access the next message.

Cleared by hardware when the output mailbox has

been released.

Bit 4 = FOVR FIFO Overrun

- Read/Clear

This bit is set by hardware when a new message

has been received and passed the filter while the

FIFO was full.

This bit is cleared by software.

Bit 3 = FULL FIFO Full

- Read/Clear

Set by hardware when three messages are stored

in the FIFO.

This bit can be cleared by software writting a one

to this bit or releasing the FIFO by means of

RFOM.

Bit 2 = Reserved. Forced to 0 by hardware.

Bit 1:0 = FMP[1:0] FIFO Message Pending

- Read

These bits indicate how many messages are

pending in the receive FIFO.

FMP is increased each time the hardware stores a

new message in to the FIFO. FMP is decreased

each time the software releases the output mail-

box by setting the RFOM bit.

CAN INTERRUPT ENABLE REGISTER (CIER)

All bits of this register are set and cleared by soft-

ware.

Read / Write

Reset Value: 0000 0000 (00h)

Bit 7 = WKUIE Wake-Up Interrupt Enable

0: No interrupt when WKUI is set.

1: Interrupt generated when WKUI bit is set.

Bit 6:4 = Reserved. Forced to 0 by hardware.

Bit 3 = FOVIE FIFO Overrun Interrupt Enable

0: No interrupt when FOVR bit is set.

1: Interrupt generated when FOVR bit is set.

Bit 2 = FFIE FIFO Full Interrupt Enable

0: No interrupt when FULL bit is set.

1: Interrupt generated when FULL bit is set.

Bit 1 = FMPIE FIFO Message Pending Interrupt

Enable

0: No interrupt on FMP[1:0] bits transition from 00b

to 01b.

1: Interrupt generated on FMP[1:0] bits transition

from 00b to 01b.

Bit 0 = TMEIE Transmit Mailbox Empty Interrupt

Enable

0: No interrupt when RQCPx bit is set.

1: Interrupt generated when RQCPx bit is set.

RFOM FOVR

FULL

FMP1

FMP0

WKUIE

FOVIE0

FFIE0

FMPIE0

TMEIE

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