sames

SA9904B

6/12

http://www.sames.co.za

Figure 8: SPI waveforms

and the SCK pin of the SA9904B. The DI and DO pins are the

serial data input and output pins for the SA9904B, respectively.

Table 1 lists the various register addresses. The SA9904B

contains nine 24 bit- registers representing the active energy,

reactive energy and the mains voltage for each phase. A tenth

24 bit register represents the mains frequency for any valid

phase. To remain compatible with the SA9604A three

addresses have been included. Any of the three addresses can

be used to access the frequency register.

Register Access

ID

1

2

3

4

5

6

7

8

9

10

11

12

Register

Active Phase 1

Reactive Phase 1

Voltage Phase 1

Frequency

Active Phase 2

Reactive Phase 2

Voltage Phase 2

Frequency

Active Phase 3

Reactive Phase 3

Voltage Phase 3

Frequency

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

0

0

0

0

A5

X

X

X

X

X

X

X

X

X

X

X

X

A4

X

X

X

X

X

X

X

X

X

X

X

X

A3

0

0

0

0

0

0

0

0

1

1

1

1

A2

0

0

0

0

1

1

1

1

0

0

0

0

A1

0

0

1

1

0

0

1

1

0

0

1

1

A0

0

1

0

1

0

1

0

1

0

1

0

1

Header

bits

The 9 bits needed for register addressing can be padded with

leading zeros when the micro-controller requires a 8 bit SPI

word length. The following sequence is valid:

Figure 8 shows the SPI waveforms and figure 9 the timing

information. After the least significant digit of the address has

been entered on the rising edge of SCK, the output DO goes

low with the falling edge of SCK. Each subsequent falling edge

transition on the SCK pin will validate the next data bit on the

DO pin.

The content of each register consists of 24 bits of data. The

MSB is shifted out first.

Data format

10

11

12

13

14

15

987654321 0

0000000110 A5 A4 A3 A2A1 A0

1

1

A5

A0

A1

A2

A3

A4

0

D23

D22

D21

D1

D0

D23

D22

D1

D0

DO

DI

SCK

CS

Read command

Register address

Register Data

Next data register

High impedance

0

Dr-01647

The header bits 110 (0x06) must precede the 6-bit address of the

register being accessed. When CS is HIGH, data on pin DI is

clocked into the SA9904B on the rising edge of SCK. Figure 8

shows the data clocked into DI comprising of 110A5A4A3A2

A1 A0. Address locations A5 and A4 are included for

compatibility with future developments.

Registers may be read individually and in any order. After a

register has been read, the contents of the next register value

will be shifted out on the DO pin with every SCK clock cycle. Data

output on DO will continue until CS is inactive.

t1

t5

t3

SCK

DI

DO

CS

DR-01545

t4

t2

Parameter

t1

t3

t4

t2

t5

Max

1.160µs

Min

625ns

625ns

625ns

20ns

625ns

Description

SCK rising edge to DO valid

SCK min high time

SCK min low time

Setup time for DI and CS

before the rising edge of SCK

DI hold time

Figure 9: SPI Timing diagrams with timing information

Table 1: Register address