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M68AF511A

Write Mode

The M68AF511A is in the Write mode whenever

the W and E pins are Low. Either the Chip Enable

input (E) or the Write Enable input (W) must be de-

asserted during Address transitions for subse-

quent write cycles. Write begins with the concur-

rence of Chip Enable being active with W low.

Therefore, address setup time is referenced to

respectively, and is determined by the latter occur-

ring edge.

The Write cycle can be terminated by the earlier

rising edge of E, or W.

if the Output is enabled (E = Low and G = Low),

then W will return the outputs to high impedance

to avoid bus contention in this type of operation.

rising edge of E, whichever occurs first, and re-

Figure 10. Write Enable Controlled, Write AC Waveforms

Note: 1. During this period DQ0-DQ7 are in output state and input signal should not be applied.

AI05913

tAVAV

tWHAX

tDVWH

DATA INPUT

A0-A18

E

W

DQ0-DQ7

VALID

tAVWH

tELWH

tWLWH

tAVWL

tWLQZ

tWHDX

tWHQX