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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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EP5348UI bảng dữ liệu(PDF) 10 Page - Altera Corporation |
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EP5348UI bảng dữ liệu(HTML) 10 Page - Altera Corporation |
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10 / 12 page  EP5348UI Figures 4 and 5 show critical PCB top and bottom layer components and traces for a minimum-footpint recommended EP5348 layout with ENABLE tied to VIN. Alternate ENABLE configurations need to be connected and routed according to specific customer application. This layout consists of four layers. For the other 2 layers and the exact dimensions, please see the Gerber files at www.altera.com/enpirion. The recommendations given below are general guidelines. Customers may need to adjust these according to their own layout and manufacturing rules. Recommendation 1: Input and output filter capacitors should be placed on the same side of the PCB, and as close to the EP5348UI package as possible. They should be connected to the device with very short and wide traces. Do not use thermal reliefs or spokes when connecting the capacitor pads to the respective nodes. The +V and GND traces between the capacitors and the EP5348UI should be as close to each other as possible so that the gap between the two nodes is minimized, even under the capacitors. Recommendation 2: The system ground plane should be the first layer immediately below the surface layer. This ground plane should be continuous and un-interrupted below the converter and the input/output capacitors. Please see the Gerber files at www.altera.com/enpirion. Recommendation 3: Multiple small vias should be used to connect ground terminal of the input capacitor and output capacitors to the system ground plane. It is preferred to put these vias along the edge of the GND copper closest to the +V copper. These vias connect the input/output filter capacitors to the GND plane, and help reduce parasitic inductances in the input and output current loops. See Figure 4. If the two vias cannot be put under CIN or COUT, then put two vias right after the capacitors next the VIN and VOUT vias. Recommendation 4: As Figure 5 shows, RA, RB, and CA have been placed on the back side to minimize the footprint. These components also need to be close to the VFB pin (see Figures 3, 4 and 5). The VFB pin is a high- impedance, sensitive node. Keep any trace connected to this node as short and thin as possible. Whenever possible, connect RB directly to the AGND pin instead of going through the GND plane. In the layout shown above, RB goes to the via next to AGND pin using a dedicated trace on layer 3 not shown here. Please see the Gerber files at www.altera.com/enpirion. Recommendation 5: AVIN is the power supply for the small-signal control circuits. It should be connected to the input voltage at a quiet point. In Figure 4 this connection is made at the vias just before CIN. There is an additional decoupling capacitor CAVIN for AVIN which is connected between the device pin and the GND plane. Recommendation 6: The via to the right of pin 2 underneath the device helps to minimize the parasitic inductances in the input and output loop ground connections. Recommendation 7: The top layer 1 metal under the device must not be more than shown in Figure 4. As with any switch-mode DC/DC converter, try not to run sensitive signal or control lines underneath the converter package on other layers. Recommendation 8: The VOUT sense point should be just after the last output filter capacitor. Keep the sense trace short in order to avoid noise coupling into the node. 10 www.altera.com/enpirion 05721 October 11, 2013 Rev D |
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