M38C2XMX datasheet(39/63 Pages) MITSUBISHI

39 / 63 page

38C2 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS

PRELIMINAR

Notice:

This

is not

a final

specification.

Some

parametric

limits

are

subject

to change.

(frequency of count source for LCDCK)

(divider division ratio for LCD)

f(LCDCK)=

f(LCDCK)

duty ratio

Frame frequency=

Fig. 37 LCD display RAM map

LCD Display RAM

The 12-byte area of address 004016 to 004B16 is the designated

RAM for the LCD display. When “1” is written to these addresses, the

corresponding segments of the LCD display panel are turned on.

LCD Drive Timing

For the LCD drive timing, type A or type B can be selected.

The LCD drive timing is selected by the timing selection bit (bit 4 of

LCD mode register).

Type A is selected by setting the LCD drive timing selection bit to “0”,

type B is selected by setting the bit to “1”. Type A is selected after

reset.

The LCDCK timing frequency (LCD drive timing) is generated inter-

nally and the frame frequency can be determined with the following

equation;

s Note

(1) When the STP instruction is executed, the following bits are

cleared to “0”;

• LCD enable bit (bit 3 of LCD mode register)

• Bits other than bit 6 of the LCD power control register.

(2) When the voltage is applied to VL1 to VL3 by using the external

resistor, write “102” to dividing resistor for LCD power selection bits

(RSEL) of the LCD power control register (address 3816).

COM3 COM2 COM1 COM0

Bit

Address

543

004016

004116

004216

004316

004416

004516

004616

004716

004816

004916

004A16

004B16

SEG1

SEG3

SEG5

SEG7

SEG9

SEG11

SEG13

SEG15

SEG17

SEG19

SEG21

SEG23

SEG0

SEG2

SEG4

SEG6

SEG8

SEG10

SEG12

SEG14

SEG16

SEG18

SEG20

SEG22

COM3 COM2 COM1 COM0

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