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IR1176

Fig. 3 Gate drive characteristics and definitions

Phase Lock Loop Design Equations:

1 - Resistor to set VCO Ceter Frequency:

Example (A): Choose Vchgpump = 1.5V, desired frequency (fvco) = 300KHz

Rvco = [1E2 x 1.5 /300] x 62 Hz = 31 KΩ

2 - Small Signal gain for VCO:

Kvco_ac (KHz/Volt) = 1E2 x Kvco_dc (KHz/Volt)/Rvco(KΩ)

Example (B): Choosing same conditions as in example A:

Kvco_ac = 1E2 x 62 / 31 = 200 KHz/volt