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IDT74LVC245ASO bảng dữ liệu(PDF) 2 Page - Integrated Device Technology |
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IDT74LVC245ASO bảng dữ liệu(HTML) 2 Page - Integrated Device Technology |
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2 / 6 page ![]() INDUSTRIALTEMPERATURERANGE 2 IDT74LVC245A 3.3V CMOS OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS PIN CONFIGURATION NOTE: 1. As applicable to the device type. Symbol Parameter(1) Conditions Typ. Max. Unit CIN Input Capacitance VIN = 0V 4.5 6 pF COUT Output Capacitance VOUT = 0V 5.5 8 pF CI/O I/O Port Capacitance VIN = 0V 6.5 8 pF CAPACITANCE (TA= +25°C, F = 1.0MHz) Symbol Description Max Unit VTERM Terminal Voltage with Respect to GND –0.5 to +6.5 V TSTG Storage Temperature –65 to +150 °C IOUT DC Output Current –50 to +50 mA IIK Continuous Clamp Current, –50 mA IOK VI < 0 or VO < 0 ICC Continuous Current through each ±100 mA ISS VCC or GND ABSOLUTE MAXIMUM RATINGS(1) NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. SOIC/ SSOP/ QSOP/ TSSOP TOP VIEW 2 3 1 A1 VCC 16 15 14 B4 B3 B5 B1 B2 11 B7 B6 B8 19 18 20 17 13 12 DIR 5 6 A6 7 A4 A5 4 A2 A3 8 9 GND 10 A7 A8 OE NOTES: 1. H = HIGH Voltage Level X = Don’t Care L = LOW Voltage Level Z = High-Impedance Inputs OE DIR Outputs L L Bus B Data to Bus A L H Bus A Data to Bus B HX Z FUNCTION TABLE(1) Pin Names Description OE Output Enable Input (Active LOW) DIR Direction Control Input A x Side A Inputs or 3-State Outputs B x Side B Inputs or 3-State Outputs PIN DESCRIPTION |
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