HT46C64 datasheet(20/47 Pages) HOLTEK

20 / 47 page

HT46R64/HT46C64

Rev. 1.40

September 21, 2004

The I/O function of PA0/PA1 are shown below.

PA0 I/O

OOOOOOOO

PA1 I/O

OOOOO

PA0 Mode

X C B

B C BBBB

PA1 Mode

X C X

X C C C B

PA0 Data

X D

1 D0 0101

PA1 Data

X D X

X D1 D D X

PA0 Pad Status

B D0 0B0B

PA1 Pad Status

I D1 DD 0 B

Note:

²I² input; ²O² output

²D, D0, D1² Data

²B² buzzer option, BZ or BZ

²X² don¢t care

²C² CMOS output

The PB can also be used as A/D converter inputs. The

A/D function will be described later. There is a PWM

function shared with PD0/PD1/PD2/PD3. If the PWM

function is enabled, the PWM0/PWM1/PWM2/PWM3

signal will appear on PD0/PD1/PD2/PD3 (if

PD0/PD1/PD2/PD3 is operating in output mode). Writ-

ing

²1² to PD0~PD3 data register will enable the PWM

output function and writing

²0² will force the PD0~PD3 to

remain at

²0². The I/O functions of PD0/PD1/PD2/PD3

are as shown.

I/O

Mode

I/P

(Normal)

O/P

(Normal)

I/P

(PWM)

O/P

(PWM)

PD0

PD1

PD2

PD3

Logical

Input

Logical

Output

Logical

Input

PWM0

PWM1

PWM2

PWM3

It is recommended that unused or not bonded out I/O

lines should be set as output pins by software instruction

to avoid consuming power under input floating state.

The definitions of PFD control signal and PFD output

frequency are listed in the following table.

Timer

Preload

Value

PA3 Data

PA3 Pad

State

PFD

Frequency

OFF

PFD

fTMR/[2

´(M-N)]

Note:

²X² stands for unused

²U² stands for unknown

²M² is ²256² for PFD0 or ²65536² for PFD1

²N² is preload value for timer/event counter

²fTMR² is input clock frequency for timer/event

counter

PWM

The microcontroller provides 4 channels (6+2)/(7+1)

(dependent on options) bits PWM output shared with

PD0/PD1/PD2/PD3. The PWM channels have their data

registers denoted as PWM0 (1AH), PWM1 (1BH),

PWM2 (1CH) and PWM3 (1DH). The frequency source

of the PWM counter comes from fSYS. The PWM regis-

ters are four 8-bit registers. The waveforms of PWM out-

puts are as shown. Once the PD0/PD1/PD2/PD3 are

selected as the PWM outputs and the output function of

PD0/PD1/PD2/PD3 are enabled (PDC.0/PDC.1/

PDC.2/PDC.3=

²0²), writing ²1² to PD0/PD1/PD2/PD3

V D D

P F D E N

( P A 3 )

O P 0 ~ O P 7

I N T 0 f o r P D 4 o n l y

I N T 1 f o r P D 5 o n l y

T M R 0 f o r P D 6 o n l y

T M R 1 f o r P D 7 o n l y

S y s t e m W a k e - u p

( P A o n l y )

R e a d D a t a R e g i s t e r

P A 0 / P A 1 / P A 3 / P D 0 / P D 1 / P D 2 / P D 3

C K

C o n t r o l B i t

P U

D a t a B u s

W r i t e C o n t r o l R e g i s t e r

C h i p R e s e t

R e a d C o n t r o l R e g i s t e r

W r i t e D a t a R e g i s t e r

D a t a B i t

P A 0 / B Z

P A 1 / B Z

P A 2

P A 3 / P F D

P A 4 ~ P A 7

P B 0 / A N 0 ~ P B 7 / A N 7

P D 0 / P W M 0

P D 1 / P W M 1

P D 2 / P W M 2

P D 3 / P W M 3

P D 4 / I N T 0

P D 5 / I N T 1

P D 6 / T M R 0

P D 7 / T M R 1

B Z / B Z / P F D / P W M 0 / P W M 1 / P W M 2 / P W M 3

Input/Output Ports

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