13

®

DAC7714

Note that CS and CLK are combined with an OR gate and

the output controls the serial-to-parallel shift register inter-

nal to the DAC7714 (see the block diagram on the front of

this data sheet). These two inputs are completely inter-

changeable. In addition, care must be taken with the state of

CLK when CS rises at the end of a serial transfer. If CLK is

LOW when CS rises, the OR gate will provide a rising edge

to the shift register, shifting the internal data one additional

bit. The result will be incorrect data and possible selection of

the wrong DAC.

If both CS and CLK are used, then CS should rise only when

CLK is HIGH. If not, then either CS or CLK can be used to

operate the shift register. See Table III for more information.

DIGITAL INTERFACE

Figure 4 and Table I provide the basic timing for the

DAC7714. The interface consists of a serial clock (CLK),

serial data (SDI), and a load DAC signal (LOADDACS). In

addition, a chip select (CS) input is available to enable serial

communication when there are multiple serial devices. An

asynchronous reset input (RESET) is provided to simplify

start-up conditions, periodic resets, or emergency resets to a

known state.

The DAC code and address are provided via a 16-bit serial

interface (see Figure 4). The first two bits select the DAC

register that will be updated when LOADDACS goes LOW

(see Table II). The next two bits are not used. The last 12 bits

is the DAC code which is provided, most significant bit first.

FIGURE 3. Basic Dual-Supply Operation of the DAC7714.

NOTE: (1) As configured, RESET LOW sets all internal registers to code 800

If RESETSEL is LOW, RESET LOW sets all internal registers to code 000

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

V

CC

V

OUTD

V

OUTC

V

REFL

V

REFH

V

OUTB

V

OUTA

V

SS

RESETSEL

RESET

LOADDACS

NIC

CS

CLK

SDI

GND

Update Selected Register

Chip Select

Clock

Serial Data In

DAC7714

0.1

µF

0.1

µF

–10V to +10V

1

µF to 10µF

+15V

–15V

+

0.1

µF

1

µF to 10µF

+

–10V to +10V

–10.0V

0.1

µF

+10.0V

–10V to +10V

–10V to +10V

+5V

FIGURE 2. Basic Single-Supply Operation of the DAC7714.

NOTE: (1) As configured, RESET LOW sets all internal registers to code 000

If RESETSEL is HIGH, RESET LOW sets all internal registers to code 800

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

V

CC

V

OUTD

V

OUTC

V

REFL

V

REFH

V

OUTB

V

OUTA

V

SS

RESETSEL

RESET

LOADDACS

NIC

CS

CLK

SDI

GND

Update Selected Register

Chip Select

Clock

Serial Data In

DAC7714

0.1

µF

0.1

µF

0V to +10.0V

1

µF to 10µF

+15V

+

0V to +10.0V

0V to +10.0V

0V to +10.0V

+10.000V